IC Design Blog

Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks. Electrical rules are relatively complex, non-standard, and growing in number and type, creating a … Read More

Low Power, PERC, ERC, thin oxide, Verification

Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for … Read More

ESD, PERC, Calibre