Posted Nov 20, 2009, by David Abercrombie
In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More
Tags:
Power,
Physical Verification,
Yield,
Design Quality,
Design for Manufacturing,
IC Verification,
Leakage,
DRC,
IC Design
Posted Jul 28, 2009, by David Abercrombie
Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More
Tags:
IC Verification,
IC Design,
Yield,
Design Quality,
Design for Manufacturing,
DAC,
Design Rules,
Leakage,
DRC,
Physical Verification,
Power,
Design Rule Checking
