Sign In
Forgot Password?
Sign In | | Create Account

IC Design Blog

Posts tagged with 'Productivity'

15 Jan, 2014

How Do I?

Posted by Shelly Stalnaker

Shelly Stalnaker It happens all the time, to all of us. You need a quick answer for a very specific question about using your EDA tools. You don’t want to wade through technical documentation, you don’t have time for an email response, and you really don’t want to try searching EDA forums for an answer. We feel your pain, and we decided to do something about it. Need to know how to extract a net from … Read More

tapeout, Debugging, Calibre, Productivity, signoff, electrical verification, Physical Verification

28 Jan, 2010

Michael White Design rule checking (DRC) or physical verification used to be easy.  For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go.  These checks were simple to write, fast to run and understandable, and quick to debug.  Today is a new world order, where none of these attributes are true anymore.  An increasing number of checks are 2-D, very … Read More

IDM, IC Design, Pattern Matching, SoC, eqDRC, Calibre, Physical Verification, Fabless, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite

15 Jan, 2010

Michael White Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass.  Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out.  Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC

Tags

Archives

 
Online Chat