This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More
Tags: Redundancy, CAA, SoC, SRAM
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
Tags: IDM, IC Design, Pattern Matching, EDA, SoC, eqDRC, Calibre, Fabless, Physical Verification, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags: Foundry, Foundries, IC Design, DRC, SVRF, EDA, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC
