Posted Jan 15, 2010, by Michael White
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags:
Foundry,
Foundries,
IC Design,
DRC,
SVRF,
EDA,
Tax,
Waiver,
Calibre,
Physical Verification,
Fab-lite,
Productivity,
Fabless,
Sign-off,
eqDRC,
SoC,
Equation-Based DRC
Posted Dec 17, 2009, by Michael White
Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers.
Why Do Competing PV Products Want to Use Calibre SVRF?
Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More
Tags:
Foundries,
Fabless,
Foundry,
TVF,
Translators,
Direct Read,
PV,
DRC,
Sign-off,
SVRF,
Calibre,
Syntax,
IC Design,
Equation-Based DRC,
IDM,
Fab-lite,
Native Read,
EDA,
Physical Verification,
eqDRC
