Stop Paying the DRC Waiver Productivity Tax
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags: Foundry, Foundries, IC Design, DRC, SVRF, EDA, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC