Posted Nov 20, 2009, by David Abercrombie
In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More
Tags:
Power,
Physical Verification,
Yield,
Design Quality,
Design for Manufacturing,
IC Verification,
Leakage,
DRC,
IC Design
Posted Aug 20, 2009, by David Abercrombie
I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More
Tags:
Reliability,
IC Verification,
Yield,
Design Quality,
Design for Manufacturing,
Scoring,
Design Rules,
IC Design,
Physical Verification,
Design Rule Checking
Posted Aug 6, 2009, by David Abercrombie
My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP.
It started … Read More
Tags:
Design Quality,
Design for Manufacturing,
IP,
Physical Verification,
Yield
Posted Jul 31, 2009, by David Abercrombie
Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More
Tags:
Reliability,
IC Verification,
Yield,
Physical Verification,
Design for Manufacturing,
DAC,
DRC,
IC Design,
Improvability,
Design Rule Checking,
Design Rules
Posted Jul 28, 2009, by David Abercrombie
Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More
Tags:
IC Verification,
IC Design,
Yield,
Design Quality,
Design for Manufacturing,
DAC,
Design Rules,
Leakage,
DRC,
Physical Verification,
Power,
Design Rule Checking
Posted Jun 19, 2009, by David Abercrombie
One of the fundamental questions everyone asks about DFM is “why should I do it?”
On the one hand this always strikes me as a funny question. I always look at DFM in the same way I think of automobile safety. Statistically, most people never get in a serious accident. So why would you spend so much money on airbags, antilock brakes, better seat belts, side door reinforcements, traction control, etc. … Read More
Tags:
Yield,
Design Quality,
Design for Manufacturing,
IC Verification,
Reliability,
Physical Verification,
IC Design
Posted Jun 5, 2009, by David Abercrombie
I got a kick out of Rohan’s comment on my previous blog (How do you define DFM?). It is too easy to assume that anyone knows what you are talking about when you say DFM. Just because everyone has been talking about it doesn’t mean any of them know what they are talking about.
You could probably infer from my approach to the previous blog that my background is primarily on the manufacturing side. … Read More
Tags:
Design Quality,
Design for Manufacturing,
Reliability,
Yield,
IC Design,
IC Verification
