Sign In
Forgot Password?
Sign In | | Create Account

Calibre Realtime

On-Demand Calibre signoff verification in custom/AMS design flows

Calibre RealTime® delivers Calibre signoff verification on demand inside the custom/AMS design creation process. Custom and analog designers can now verify and optimize their designs against Calibre signoff decks while they edit their layouts. With Calibre RealTime, designers can improve both design speed and the quality of results.

Calibre RealTime delivers signoff-quality Calibre design rule checking (DRC) inside custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.

Major Features

  • Uses standard foundry-qualified Calibre rule decks
  • Automatically runs Calibre nmDRC when edits are made in layout
  • Provides built-in error review toolbar to enhance ease of use
  • Uses OpenAccess run-time model to enable integration with most custom design environments
  • Employs in-memory checking to ensure best performance
  • Supports user-defined custom filters tied to layout interface
  • Complements existing built-in checkers

Supported Integrations

  • Springsoft Laker™ design environment (version OA 2010.8)
  • IC Station® (version v10).

Benefits

  • Allows interactive editing of custom/AMS designs based on Calibre signoff rule decks, ensuring DRC-clean designs
  • Provides instantaneous feedback on DRC violations during layout creation and editing, enabling quick and accurate correction of the most complex configurations
  • Enables more design optimization during layout creation, resulting in better quality and higher performance
  • Reduces overall design cycle time by eliminating verification iterations
  • Increases designer productivity by providing more time and information during the design creation process
  • Runs within the custom design tool as an integral part of design creation flow

What Others Are Saying

The tool was clearly designed by someone with first-hand analog layout experience in that it never seems to be in the way, but yet is always available to be used when and how the designer wants to use it.”

Ted Buchwald, a senior engineer at Mobius Semiconductor

The new flow is seamless and virtually instantaneous, allowing our designers to use foundry-qualified verification information during design optimization in real time. We believe that we can save at least a week on a typical implementation project with this flow.”

Richard Rouse, director of CAD at MoSys, Inc.

By eliminating iterations, data transfer delays, and ripple effects that are common when physical verification is left until later in the cycle, designers can get sign-off quality feedback in real time and shorten the overall design cycle.”

JT Li, VP of Physical Design & Technology Product Group at Springsoft

 
Online Chat