Delivers unparalleled performance on ASIC, memory, analog, SoC designs, etc. with no trade-off in accuracy
Single rule file can drive DRC, LVS, and Calibre xRC functionality
Reads LVS data structures to integrate parasitic information with intentional circuit elements
Model-based engine calculates intrinsic and coupling capacitances for all nets using the same high degree of accuracy
Integrates with Calibre DRC and LVS, Calibre Interactive, Calibre View and Calibre RVE, which offer powerful verification and cross-probing capabilities
Benefits:
Extraction and simulation results correlate closely with silicon measurements
Offers AMS SoC designers a single parasitic extraction solution that is independent of design style or flow
