Chip-Level Floorplan & Place & Route
| IC Station provides mixed-signal floorplan editing and chip assembly capabilities built into a unified full-featured custom block layout editor -- this makes for seamless custom layout from the chip to the device level. | |
| In a top-down flow, users can estimate block areas, define block sizes and shapes, analyze congestion, assign pins, integrate pre-defined IPs and digital blocks, and route critical nets and busses. | |
Chip assembly can be performed rapidly using IC Station's in-built shape-based and constraint-driven automatic area router. In-line integration to Calibre DRC/LVS enables easy layout verification and finishing.
- Olympus SoC
The Olympus-SoC solution delivers innovative technologies for 65 and 45 nm processes. It provides the next-generation place and route system that concurrently addresses variations in lithography, process corners, and design modes. Integral to Olympus-SoC is Mentor’s detailed routing architecture which embeds variation-aware timing, optimization and litho-modeling to address optical proximity correction (OPC) and resolution enhancement technology (RET) effects early in the design cycle ensuring faster timing closure for complex process rules. It is capable of simultaneously solving for dozens of different process corners and design modes, ensuring an optimized chip without unnecessary guard banding.
- Pinnacle
The Pinnacle suite provides the fastest and the best design for variability implementation solution for the biggest chips. Built on revolutionary platform architecture Pinnacle delivers the best performance Design for Variability (DFV) engine, handles extremely large designs, and plugs seamlessly into existing design flows. Rapid Physical Feasibility features help engineers in the early design phase to refine and finalize the floor plan and respond to complex design constraints.
- Calibre DESIGNrev
Calibre DESIGNrev offers fast loading and visualization of multi-gigabyte GDSII layout data.
- IC Station SDL
The IC Station® Tool Suite provides the physical layout component of the Mentor Graphics full custom IC design flow. This suite includes application bundles for editing, schematic-driven layout, and top-level floor planning/routing.
Events
Meeting the Critical Challenges of IC Implementation
Learn about the evolution of Mentor's comprehensive Design-to-Silicon IC implementation solution.
Accelerating Custom IC Layout with IC Station
Come and learn how to accelerate your custom layout while maintaining flexibility and custom quality. In this technical hands-on workshop, you will use Mentor's layout editor, integrated routers, and verification solutions to take a design from schematic to DRC-correct layout in a fraction of the time.
Online Demo: Accelerating Custom IC Implementation: Speed Without Compromise
This video demonstrates how Mentor's IC Station custom layout platform, with its tight integration to schematic capture and Calibre verification, can help you get the layout quality and speed you need, without compromise.
