Olympus-SoC
Olympus-SoC™ is a complete IC implementation (netlist-to-GDSII) solution targeted at 65nm/45nm designs, which augments Mentor Pinnacle™, the industry’s leading Design for Variability solution.
Olympus-SoC gives designers the ability to optimize designs subject to variations in design modes, as well as lithography and other manufacturing processes windows, in a comprehensive and holistic fashion. Advanced multi-corner, multi-mode, (MCMM) technology provides timing optimization across a large number of design and process corners throughout the design flow, ensuring fast design-for-manufacturing closure. Integral to Olympus-SOC is Mentor's next-generation detailed routing architecture that incorporates variation-aware timing optimization and litho-modeling to address OPC/RET effects early in the design cycle.
With its high capacity implementation architecture, Olympus-SoC provides these advanced capabilities even for the largest designs at 45nm and beyond.
Benefits
- Lithography driven routing with embedded timing optimization — Improves yield by addressing lithography issues in a timing context during design implementation.
- Adaptive variability engine — Concurrently analyzes and optimizes for variations in Lithography, Process Corners, and Design Modes for best results and rapid closure.
- OptRoute Engine — Live interaction between optimization and detailed routing for reduced ECO iterations and faster time to market.
- Small memory footprint database - Compact model data representation handles multi-million gate designs and enables faster runtimes.
Product Resources
Technical Papers
IC Resources
Other Resources
Features
Architecture
Innovative Architecture
- Ultra compact and flexible open architecture
- Fast, accurate, and incremental signoff quality timer
- Incremental and on-the-fly parasitic extraction
- Supports standard cell and structured ASIC
- Powerful query language and full TCL scripting environment
Floorplanning
Floorplanning & Rapid Feasibility
- Supports many levels of logical and physical hierarchies
- Full support for hard/soft regions with automatic conversion to partitions
- Black-box modeling for early floorplanning
- Rapid constraint debug environment
- Simultaneous standard cell and hard macro placement
- On-the-fly folding and unfolding of blocks instantiated multiple times
Synthesis
Physical Synthesis
- Intelligent netlist preconditioning
- Unique global bottleneck analysis engine
- Powerful analytical local and global optimization
- OCV (On Chip Variation) Modeling in Optimization
- Common Path Pessimism Removal during Hold Optimization
- Fast, accurate global router with trial route capabilities
Clock Tree Synthesis
- Automatic skew/insertion delay optimization
- Clone/Declone technology of clock gate cells
- Automatic clock tree synthesis of complex cascaded gating logic
- Support for modes, corners, and OCV derating
- Clock-gate re-location and sizing
- Useful skew optimization
Lithography
Lithography Driven Routing
- 65nm-ready litho-driven detailed router integrated into Mentor's proven Design for Variability system
- Built from the ground-up to eliminate manufacturing errors such as litho pinching/bridging faults, notches, min-area metal extensions, etc.
- Unique OptRoute engine enables "live" interaction between optimization and routing
- Detailed sign-off level analysis integrated into routing engine
- Fast, Multi-CPU router with powerful ECO capabilities
Variability
Design for Variability
- Simultaneous and concurrent analysis and optimization of multiple scenarios
- Any number of mode/corner combinations supported
- Automatic and dynamic CRPR analysis and optimization for setup/hold/noise
- Accurate hold-fixing with “multimoment” delay calculation
Low Power/Signal Integrity
Low Power
- Concurrent timing and leakage optimization
- Supports complex clock gating structures in CTS, placement, optimization
- Multi-voltage / multi-threshold
Signal Integrity
- Signal Integrity Prevention and repair flows
- Built-in glitch analysis and optimization
- Crosstalk delta-delay analysis & optimization (logical & physical)