This is what our clients have to say about us...
"We used Sierra Pinnacle for prototyping and physical synthesis and clock tree placement of the complete chip. During the prototyping phase, Sierra was used to quickly analyze various floorplans and identify missing constraints. During the implementation phase, Pinnacle successfully exceeded the performance targets: operating 10 percent faster, using two watts less power, and reducing buffer count while concurrently optimizing at eight process corners. In addition to reducing the number of iterations, Sierra's run times were also very impressive: 30 minutes for a prototyping run and about four hours for an implementation run. Pinnacle enabled us to achieve high performance quickly by minimizing the number of iterations for large complex chips."
"Fujitsu is continually addressing our customer needs by upgrading our IC implementation flows to achieve rapid closure on large designs efficiently, and to satisfy the design requirements of 90 nanometer processes and emerging smaller geometries. Sierra's physical design system has demonstrated the capacity, speed and implementation quality needed for our ASIC designs. Fujitsu is incorporating Pinnacle's physical design system into our IC implementation flow. Additionally, we are analyzing Pinnacle's flexible product architecture for use with AccelArrayTM, Fujitsu's new ASIC design platform, and expect it will enable us to offer a very high-capacity, fast turn-around design flow for our AccelArray customers.”
"Our complex, high-performance designs demand very high quality results and fast turn-around times from our physical design implementation flow. The addition of Sierra Pinnacle to our arsenal enables our designers to meet their challenging design goals.”
"At 90nm/65nm process nodes, design size, design variability and constraint complexity are creating major challenges in term of predictability and engineering effort for IC Implementation. We are impressed with the speed and capacity of Sierra's Pinnacle system and it allows us to bridge the gap between prototyping and implementation. Sierra Pinnacle easily plugs into and complements our current flow and delivers fast turnaround for big chips.”
