Pinnacle
Pinnacle suite provides a high performance, highly scalable design-for-variability implementation solution for the largest Nanometer ICs.
Pinnacle is the industry's first IC implementation solution that comprehensively addresses the performance, capacity, time-to-market, and variability challenges occurring at the 65nm and 45nm process nodes. Built on advanced platform architecture with an embedded signoff-quality timer, Pinnacle delivers highly optimized physical designs with fast turnaround and rapid manufacturing closure. Pinnacle's Adaptive Variability Engine analyzes and optimizes the design for multiple operating modes and manufacturing process variability early in the design phase, and throughout the design-to-fab flow. Pinnacle's Rapid Physical Feasibility features help engineers in the early design phase to refine and finalize floor plans for complex design constraints. An open architecture and ultra-compact database allow Pinnacle to handle extremely large design capacities and to plug seamlessly into existing design flows.
Pinnacle can save months by accounting for a variety of late-stage design closure issues: timing problems seen at multiple operating modes or corners, on-chip variation induced setup and hold violations, power issues seen later in design flow due to multi-corner and multi-mode fixing, and clock tree synthesis related congestion. Pinnacle gives designers the ability to evaluate implementations early in the design cycle.
Benefits
- Assesses physical designs across multiple design contexts and multiple manufacturing process windows.
- Built-in timing analysis ensures optimized designs throughout the implementation process.
- Quickly refines and finalizes floor plans for complex design constraints.
- Fast time-to-results with multi-corner, multi-mode analysis that reduces the number of iterations required to reach design closure.
- High performance even on extremely large designs.
Product Resources
Technical Papers
IC Resources
Other Resources
Pinnacle Features
Floorplanning/Feasibility
Floorplanning & Rapid Feasibility
- Integrated feasibility and implementation engines
- Support for many levels of logical and physical hierarchies
- Full support for hard/soft regions with automatic conversion to partitions
- Black-box modeling for early floorplanning
- Rapid constraint debug environment
- Simultaneous standard cell and hard macro placement
- On-the-fly folding and unfolding of blocks instantiated multiple times
Synthesis
Physical Synthesis
- Intelligent netlist preconditioning
- Unique global bottleneck analysis engine
- Powerful analytical local and global optimization
- OCV (On Chip Variation) Modeling in Optimization
- Common Path Pessimism Removal during Hold Optimization
- Fast, accurate global router with trial route capabilities
Clock Tree Synthesis
- Automatic skew/insertion delay optimization with best quality of results
- Automatic clock tree synthesis of complex cascaded gating logic
- Support for modes, corners, and OCV derating
- Clock-gate re-location and sizing
- Useful skew optimization
Architecture
Interface
- Input: DEF, PDEF, Verilog, .lib, SDC, LEF
- Output: DEF, PDEF, SPEF, Verilog
Innovative Architecture
- Ultra compact and flexible open architecture
- Fast, accurate, and incremental signoff quality timer
- Incremental and on-the-fly parasitic extraction
- Supports standard cell and structured ASIC
- Supports flat and hierarchical flows
- Powerful query language and full TCL scripting environment
- Open-GL based GUI
- Complete support for logical/physical hierarchy
Variability
Design for Variability
- Simultaneous and concurrent analysis and optimization of multiple scenarios
- Any number of mode/corner combinations supported
- Automatic and dynamic CRPR analysis and optimization for setup/hold/noise
- Accurate hold-fixing with “multimoment” delay calculation
Low Power/Signal Integrity
Low Power
- Concurrent timing and leakage optimization
- Supports complex clock gating structures in CTS, placement, optimization
- Multi-voltage / multi-threshold
Signal Integrity
- Signal Integrity Prevention and repair flows
- Built-in glitch analysis and optimization
- Crosstalk delta-delay analysis & optimization (logical & physical)