Pinnacle: Product Highlights

Pinnacle supports very fast physical feasibility analysis early in the design cycle. Designers can quickly establish the likelihood of the chip meeting its specifications, including die size, speed, and power, while accounting for all late-stage design effects such as clock tree synthesis, test/BIST insertion, multiple mode/corner analyses and setup/hold effects that cause variability problems. Pinnacle also helps designers in debugging and cleaning "dirty" design constraints in the early phases of the design flow.

During the implementation phase, Pinnacle enables designers to define all the modes and corners up-front instead of choosing a worst-case mode/corner, or over-margining timing constraints. This approach eliminates the need to "over-constrain" the design or sacrifice specified targets to meet time-to-market requirements. Pinnacle optimizes for timing, area, power, and signal integrity concurrently at all the defined modes/corners. It enables designers to build clock trees for all sinks over all modes of operation and with similar skew across multiple process corners. With Pinnacle, designers can build robust clock trees that are resilient to process variation.