Design Architect IC

Design Architect-IC is a powerful tool for capturing and netlisting design data integrated within a full custom IC design flow. Design Architect-IC works with the Mentor Graphics IC Station design tools to conceptualize, develop, simulate, verify, and produce even the most challenging full custom analog and mixed-signal IC designs quickly and accurately—the first time. The designer enjoys a consistent look and feel in one environment, whether creating schematics, block diagrams, symbols or HDL representations.

Custom IC Flow

Mentor’s Custom IC flow and its integrated schematic, extraction and simulation tools allow you to take a design from system specifications to post-layout verification with a virtually seamless approach.

Schematic Capture, Simulation Setup and Analysis

Design Architect-IC shortens design cycles by creating a high productivity environment for schematic capture and simulation setup for A/MS and RF simulation and analysis. The ability to simulate analog components quickly and accurately is achieved through an interface with Mentor Graphics Eldo™ and Eldo RF, and ADVance™ MS products, creating a tight loop for capture, simulation and analysis of designs.

Verification and Simulation

Design Architect-IC interfaces seamlessly with Mentor Graphics simulation tools, enabling quick and accurate simulations of high transistor count processors, memory modules and mixed-signal designs. The result is shorter design cycles due to increased productivity.

Superior Modeling Capability

Design Architect-IC models digital, analog and mixed-signal blocks in a common environment using schematic representations C, VHDL, Verilog, SPICE, VHDL-AMS, or Verilog-AMS. Then it quickly enables simulation of the entire hierarchical design. Its ability to intelligently make trade-offs in design representations leads to faster and more accurate mixed-signal IC chip verification.

Features and Benefits

  • Shortens design cycles by increasing productivity in schematic capture, simulation setup and analysis for analog/mixed-signal (A/MS) and radio frequency (RF) designs
  • Leads to faster and more accurate mixed-signal IC verification
  • Reduces hardware costs, leveraging cost-effective Linux workstations
  • Enables higher schematic entry productivity, especially for designs with repeated circuitry

A Closer Look

This 15 minute, multimedia demo and tutorial shows how IC designers can utilize Design Architect IC (DA_IC) to easily model parasitic capacitance at each phase of the design cycle.

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DSPF Back-Annotation Flow in Design Architect IC On-demand Web Seminar

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