Pyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing.
Pyxis Layout supports an extensive set of editing functions for efficient, accurate polygon editing. This gives the design engineer full control of circuit density and performance, while improving productivity by as much as 5X. Hierarchy and advanced window management allows multiple views of the same cell and provides the capability to edit both views. Additionally, design engineers can create matched analog layouts quickly by editing using a half-cell methodology.
Pyxis Layout interacts seamlessly with other solutions in the Pyxis Custom IC Design Platform to create, develop, simulate, verify, optimize and implement even the most challenging full custom analog and mixed-signal IC designs quickly and accurately—the first time. As a designer, you enjoy a consistent look and feel in single environment, whether creating schematics, block diagrams, symbols, or HDL representations. Additionally, Mentor’s foundry partners provide certified design kits for use with Pyxis Custom IC Design Platform solutions.
Schematic Driven Layout
Schematic-driven layout (SDL) is a design methodology that enables design engineers to create "correct by construction" layouts. These layouts are based on information from a schematic or a netlist source. By using the designs connectivity, Pyxis SDL enables automated creation of layout data, while maintaining the relationship between layout and schematic, reducing design cycle time and assuring layout is free of LVS violations.
Any mix of polygons, device generators (either custom, built-in or from a foundry supplied Process Design Kit), and cell data are supported in the layout environment. Available as an add-on option to Pyxis Layout, Pyxis SDL enables this functionality, reducing design cycle time and assuring correct-by-construction layout.
Pyxis Concurrent, an add-on option for Pyxis Layout, allows multiple designers to simultaneously make edits to the same cell. With Pyxis Concurrent, multiple designers can join a layout session in shared mode. Once in the session, the designers create fences to define their work area. They can create one or more fences and can make edits to any shape or path that is wholly enclosed within their fenced area. These shapes are local to the session and are not stored with the design. For more information, please view the Pyxis Concurrent datasheet.
Signoff Quality Physical Verification
Integration with Calibre RealTime® provides Calibre signoff quality physical verification, on-demand, within Mentor’s Pyxis Custom IC Design Platform. Using the same Calibre decks as the signoff flow, custom and analog designers can now verify and optimize their designs while they edit their layouts. With Calibre RealTime, designers can optimize their layouts for performance without sacrificing manufacturing yield.
Benefits and Options
- Improves layout design throughput up to 50X compared to manual layout methods.
- Multiple tools support increasing level of layout automation.
- Reduces design rule checking (DRC) debugging cycles, leading to shortened time-to-market.
- Creates DRC/LVS–correct complex layout with a simple command to improve reliability of final product.
- Pyxis Concurrent – Adds concurrent editing functionality to Pyxis Layout
- Pyxis TFT-LCD – Adds functionality required for flat panel design to Pyxis Layout
- Pyxis Plot – Enables plotting to HP Plotter from Pyxis Layout
Custom IC Design Training
We have training courses available for Custom IC Design products in our training centers around the world, online, or at your site.
“Moving from a well entrenched design and verification environment to something new is an enormous task even when you’re not faced with an impending tapeout. Mentor put a great deal of time into anticipating possible problems, and working to dismiss them before they could manifest themselves. This attention to detail was critical to the ultimate success of the replacement process.”