At nanometer nodes, design signoff is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, and printability and performance validation, all of which Mentor addresses with the DFM tools of the Calibre nm Platform. Building on our powerful, production-proven Hyperscaling architecture, we deliver the broadest, most accurate, and best performing DFM solutions in the industry. Because the Calibre platform is built on standard open database interfaces, it brings production-proven DFM capabilities to our customers independent of the design creation environment they use.
Calibre CMPAnalyzer enhances systematic and parametric yield at smaller process nodes by simulating the changes in thickness and resistance variability, and by using automated fill capabilities to reduce... View Product Overview
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related... View Product Overview
Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield. It addresses the issue of area with a core philosophy to take advantage of any white space. This method... View Product Overview
Critical Area Analysis
Calibre YieldAnalyzer performs critical area analysis (CAA) on all base and interconnect layers of a design. CAA identifies those areas of an integrated circuit layout with higher than average vulnerability to random particle defects that can create a short or open in areas with close spacing of layout features. Calibre YieldAnalyzer also performs critical feature analysis (CFA), a flexible extension to traditional recommended rules analysis, by employing a model-based approach that automatically plugs layout measurements into yield-related equations to identify areas of a physical design that have higher sensitivity to variations across the manufacturing process window. By integrating random (CAA) and systematic (CFA) process analysis, the Calibre nm Platform accounts for the combined impact of these effects on design manufacturability and enables designers to prioritize and guide manufacturability improvement in light of a wide spectrum of yield limiters.
Calibre YieldAnalyzer’s model-based CAA/CFA methodology complements the Calibre LFD™ litho-friendly design solution. Calibre LFD provides the ability to run simulations to see how a layout will print under a particular lithographic process window. Calibre LFD allows designers to achieve an “LFD clean” as well as a “DRC clean” sign-off to ensure high yields for advanced process nodes. Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield. It implements enhancements by taking advantage of white space, improving yield without sacrificing area. To balance performance, YieldEnhancer offers both a net-aware capability and back annotation to the design database. To determine the impact on yield, YieldEnhancer works with Calibre YieldAnalyzer to measure the impact of the layout modification.
Calibre nm Platform
Mentor is continuing to extend the Calibre nm Platform to address all the needs of physical verification, DFM and post-tapeout physical design improvement. We invest heavily to ensure that our platform and tools are tightly integrated with each other and all major design environments, so users can have the flexibility to create optimum DFM flows while protecting their existing EDA investment.
Calibre DFM Features
Hierarchical Processing Engine
The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.
Custom Design and Verification Environments
Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.