Chemical-mechanical polishing (CMP) is one of the most significant and direct effects on chip success. The capability to predict and minimize CMP variation in a design is crucial to achieving your yield goals. Model-based planarity analysis enhances systematic and parametric yield at smaller process nodes by accounting for the changes in thickness and resistance variability caused by decreasing linewidths.
The complete Mentor Graphics planarity improvement solution consists of an integration of Calibre® CMPAnalyzer and Calibre YieldEnhancer software with a CMP simulator. Calibre CMPAnalyzer offers direct connection to multiple CMP simulators, including Mentor Graphics’ CMP simulator and the TSMC VCMP simulator.
Data provided by these CMP simulators to Calibre CMPAnalyzer enable designers to visually highlight and examine a variety of CMP effects. Designers can examine these results layer by layer, and for selected areas in the layout. They can also review specified CMP hotspot checks, such as depth of focus checks.
This analysis can also be combined with Calibre YieldEnhancer’s SmartFill automated fill capabilities to optimize planarity and reduce bridging due to dishing and thickness variations. The SmartFill algorithm is designed to achieve your planarity goals while minimizing the amount of fill shapes added. This combination reduces resistance variability while minimizing capacitance added by the filling process.
The thickness values generated by Calibre CMPAnalyzer can be incorporated into the Calibre xRC™ and Calibre xL tools to create a comprehensive 3D circuit model with device and interconnect parameters that more closely match silicon results. The results can drive extremely accurate simulations using Mentor’s ADiT™ or other leading circuit simulators supported by Calibre’s back annotation facilities.
Calibre CMPAnalyzer, like all the Calibre products, is built on the Calibre nm Platform, the industry’s leading physical verification platform known for delivering best-in-class performance, accuracy, and reliability.
Features and Benefits
- Ease of Use: Use one menu to set up and execute simulations, analyze results, and perform fill and extract operations
- Cost Effective: Use customized simulation models in-house and modify when and as needed
- Control Variability: Minimize fill shapes while still meeting planarity goals
- Reduce Time to Market: Combine CMP analysis and automated fill in a single operation to reduce design iterations
- Production Proven: Fully qualified at TSMC for specific TSMC technology data
Calibre RVE™-graphical results viewing environment to reduce debug time by visually identifying design errors instantly in the user’s own design environment.
Calibre DESIGNrev layout viewer speeds full-chip design completions & tape-outs by rapidly loading, displaying & saving large GDSII & OASIS® files.