Calibre® LFD™ (Litho Friendly Design) is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation. Calibre LFD accurately models the impact of lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects.
By accurately simulating the effects of the lithographic process on “as-built” layout geometry, the Calibre LFD tool enables designers to make trade-off decisions early, resulting in a design that is more robust and less sensitive to the lithographic process window. This level of analysis is important at nanometer nodes, where even small process variations can greatly influence silicon results.
Highest Potential for Yield Improvement
Calibre LFD identifies layout “hot spots,” structures with a higher probability of failing due to litho process variations, and grades them to determine which have the highest potential for yield improvement. Integration with the Olympus-SOC™ design tool enables feed-forward of Calibre LFD results to give designers guidance on recommended layout improvements, and to enable revalidation of correct timing after modifications.
Precise Lithographic Modeling
To enable Calibre LFD’s precise lithographic modeling, the foundry provides designers with an LFD kit for their process in the same manner as a design rule checking (DRC) kit. The designer can then run simulations to see an accurate description of how a layout will perform under the foundry’s specific lithographic process. The goal is to drive the design to an "LFD clean" as well as a "DRC clean" sign-off. With a Calibre LFD kit, designers can create designs and check them with foundry-specific Calibre LFD verification to ensure they are free of lithographic hot-spots before submitting them to the foundry fabrication process.
Features and Benefits
- Results in a "DRC-clean" and "LFD-clean" sign-off
- Gives users the ability to improve yield by creating a design that is less sensitive to variations in a given manufacturing process.
- Uses product-proven RET recipes and process models to simulate lithography effects.
- LFD Kit predicts and captures areas of potential design failure due to the manufacturing process and specific process conditions and communicates issues to the designer for possible layout modification.
- Design Variability Index (DVI™) provides data that helps the designer make decisions about which layout configuration is best for increased robustness to process variation.
- LFD data reporting presented in a user-friendly DRC-type form that can be classified, sorted and include comments for possible solutions, all within the design environment.
- Easily integrated into the design flow for interactive and iterative processes.
- Fully integrated with the Calibre platform, popular layout environments and industry standard formats.
Calibre RVE™-graphical results viewing environment to reduce debug time by visually identifying design errors instantly in the user’s own design environment.
Calibre DESIGNrev layout viewer speeds full-chip design completions & tape-outs by rapidly loading, displaying & saving large GDSII & OASIS® files.