As volume IC production increases in the sub-100nm nodes, manufacturing costs increase dramatically and yield is increasingly sensitive to both random and systematic defects and process variations. Calibre® YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify hot spots—areas of your physical design that have higher sensitivity to variations across the manufacturing process window. Designers can use this tool not only for critical area extraction and yield prediction, but also as a reference tool to enable more effective design enhancement.
Calibre YieldAnalyzer performs critical area analysis (CAA) on all base and interconnect layers to identify areas of a layout with excess vulnerability to random particle defects, such as shorts and opens, due to close spacing of layout features. A CAA deck is configured with the layer mappings for the designs being evaluated, and foundry estimates for the defect density distributions for each process and defect type (open/short). Calibre YieldAnalyzer then uses this CAA deck to calculate the amount of area in each layout layer that is susceptible to a short or open for a range of defect sizes. This distribution of critical area by defect size is produced for each layer and each defect type. These critical area distributions are then multiplied by the defect density distributions for the corresponding layer and defect type to determine the failure probability. These probabilities are used to identify random defect hotspots.
Critical Feature Analysis
Critical Feature Analysis (CFA) quantifies design sensitivity to a systematic issue as represented by adherence to a recommended rule. To implement CFA, a rule deck is configured with a list of recommended rules and estimates for weighting functions for each rule based on foundry recommended rule priorities. Calibre YieldAnalyzer uses this deck to generate a weighted score for each recommended rule violation.
Forward Annotated to Place & Route Tools
CAA and CFA data can be forward-annotated to P&R tools like Olympus-SoC™, automatically reducing the critical area while ensuring that correct timing is preserved. Calibre YieldEnhancer uses CAA and CFA results to automatically specify a variety of interconnect and base layer enhancements, such as via doubling, via enclosure expansion and general edge moving, to improve yield.
Features and Benefits
- Results in a "DRC-clean" and "LFD-clean" sign-off
- Gives users the ability to improve yield by creating a design that is less sensitive to variations in a given manufacturing process.
- Uses product-proven RET recipes and process models to simulate lithography effects.
- LFD Kit predicts and captures areas of potential design failure due to the manufacturing process and specific process conditions and communicates issues to the designer for possible layout modification.
- Design Variability Index (DVI™) provides data that helps the designer make decisions about which layout configuration is best for increased robustness to process variation.
- LFD data reporting presented in a user-friendly DRC-type form that can be classified, sorted and include comments for possible solutions, all within the design environment.
- Easily integrated into the design flow for interactive and iterative processes.
- Fully integrated with the Calibre platform, popular layout environments and industry standard formats.
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.
The Calibre DESIGNrev layout viewer speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.