ADMS: Mixed-Signal SoC Design and Verification Workshop
Mentor Graphics cordially invites you to attend a FREE "hands-on" Mixed-Signal Design and Verification Workshop. In this workshop we will explore the current trends of IC design and highlight the challenges these trends create. This workshop will expose you to comprehensive solutions necessary to improve your design and verification productivity.
During this lab-intensive technical workshop, you will gain first-hand experience evaluating Questa ADMS, Mentor's Mixed-Signal Simulation Solution.
Lab 1 - Getting started with ADMS
- Explore the ADMS graphical interface and infrastructure
- Run digital and mixed-signal simulations with an adder and ADC circuits
Lab 2 - Mixed-Signal Simulation: Digital-centric
- Learn about using analog SPICE circuits within a digital netlist hierarchy
- Explore the analog-digital interface and how to bridge the domains
- Understand the importance of validating analog and digital blocks together
Lab 3 - Mixed-Signal Simulation: Analog-centric
- Learn how to use HDL behavioral models within a schematic
- Observe the impact of AMS modeling on performance and functionality on a PLL circuit
Who Should Attend
- CAD managers interested in the latest mixed-signal design and verification tools
- System engineers performing verification of mixed analog and digital systems
- Analog design engineers who create IP for mixed signal ICs
Digital design engineers who are seeing analog portions entering their designs
- Project leaders who want their mixed-signal designs to meet specifications
- Modeling engineers who create models for design or verification
Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.
Using Questa ADMS in a Mixed Signal OVM Environment
Micron was able to realize a mixed-signal gray-box verification environment using OVM and the Questa® ADMS and ADiT™ simulators. Because Questa ADMS provides a robust environment that supports...
Martin Vlach at DAC 2012
Interview with Mentor Graphics' Martin Vlach at DAC 2012.
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface
Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM.