Beyond Physical Verification: Advanced Electrical Rule Checking on Layout

Web Seminar

There are currently no dates scheduled for this event. However a recording of a previous session is available as an on-demand web seminar.

View This On-Demand Web Seminar Now

Overview

This seminar will present advances in methods and tools to spot those issues, covering the requirements for effectiveness: versatility, user-friendliness, capacity for full-chip verification.

Chips designed at the latest technology nodes are prone to a variety of design errors that may not easily be identified by traditional physical verification tools. Many of these errors can result in electrical failure. Identifying and correcting these errors is critical for designers to produce working silicon.

Traditionally, designers have relied on Electrical Rule Checking (ERC) for this type of verification and most ERC methodologies combine physical verification techniques, simulation and manual checking. As designs incorporate more mixed-signal content, the complexity of checks for issues such as Electrostatic Discharge has increased, and reliance on manual checking and time-consuming simulation becomes problematic.

Schematic-based checks are not sufficient and Chip Designers need new tools that can automate schematic-driven, layout-based ERC checks to eliminate lengthy and error-prone manual checking of the physical design.

What You Will Learn

  • What are the technology drivers that are causing the need for more design verifications
  • What check automation of new physical design rules can be achieved
  • What are the expectations for verification standards driven by modern tools for Advanced Electrical Rule Checks

About the Presenter

Presenter Image Laurent Boganski

Laurent Boganski is a Product Specialist for Calibre solutions in interconnects parasitic extraction and Programmable Electrical Rule Checks. His responsibilities include supporting major customers in the area of physical verification, across Europe.

Laurent brings 20 years of experience in chip design and EDA tools support. He started his career as a design engineer at a gallium-arsenide foundry of Thales. Prior to joining Mentor 2 years ago, Laurent already worked in Grenoble at a major EDA vendor, in the area of parasitic extraction, and physical implementation of digital chips.

Laurent has an engineering degree in micro-electronics from ESIEE in Paris.

Who Should Attend

  • Design engineers
  • ESD protection engineers
  • Engineering managers

Products Covered

This web seminar is part of our Tuesday Tech Talks.
Learn More

Technical Requirements

What do I need to watch and hear this web seminar?

Mentor Graphics’ web seminars are delivered using Adobe Connect. To watch the seminar all you need to have installed is the Adobe Flash Player, version 8 or later on Windows, Macintosh, Linux, and Solaris. The Flash Player is already installed on over 98% of internet connected computers worldwide so you will not have to install any software prior to attending the meeting. You will be able to login to the seminar room 15 minutes prior to the start time on the day of the presentation. You can hear the audio using your computer’s speakers via VoIP (Voice over IP) and background music will play prior to the beginning of the presentation.

Detailed system requirements

Microsoft® Windows Vista® Home Basic, Home Premium, Ultimate, Business, or Enterprise (32-bit edition)

  • Microsoft Internet Explorer 7 or later
  • Mozilla Firefox 2
  • Adobe Flash® Player 8 or later

Microsoft Windows® XP Professional or Home Edition with Service Pack 2

  • Microsoft Internet Explorer 6, 7
  • Mozilla Firefox 1.x, 2.x
  • Mozilla 1.x or later
  • Netscape 7.x
  • Adobe Flash Player 8 or later

Microsoft Windows 2000 with Service Pack 4

  • Microsoft Internet Explorer 5.x
  • Mozilla Firefox 1.x, 2.x
  • Mozilla 1.x
  • Netscape 8
  • Adobe Flash Player 8 or later

Windows hardware requirements

  • Intel® Pentium® II 450MHz or faster processor or equivalent (1GHz recommended when screen sharing)
  • 128MB of RAM

Mac OS X v10.4, 10.5 (Intel)

  • Firefox 1.5.0.3, 2.x
  • Safari 2.x
  • Adobe Flash Player 8 or later

Mac OS X v10.4 (PowerPC®)

  • Safari 1.x, 2.x
  • Firefox 1.x
  • Mozilla 1.x
  • Netscape 7.x or later
  • Adobe Flash Player 8 or later

Mac OS hardware requirements

  • PowerPC G3 500MHz or faster or Intel Core™ Duo 1.83GHz or faster processor
  • 128MB of RAM

Linux:

  • Red Hat® Enterprise Linux® (REHL) 3 update 8; RHEL 4 update 4 (AS/ES/WS); Novell SUSE® 9.x or 10.1
  • Mozilla Firefox 1.5.0.7, 2.x
  • Mozilla 1.7.x
  • SeaMonkey 1.0.5
  • Processor: Modern processor 800MHz or faster (1GHz recommended)
  • Memory: 512MB of RAM; 128MB of graphics memory
  • Adobe Flash Player 9 or later

Solaris™

  • Mozilla 1.7
  • Adobe Flash Player 9 or later

Additional requirements

  • Minimum bandwidth 56Kbps

More Events

ADMS: Mixed-Signal SoC Design and Verification Workshop

  • ADMS: Mixed-Signal SoC Design and Verification Workshophttp://www.mentor.com/products/ic_nanometer_design/events/adms_mixed_signal_workshop May 30, 2012 : Austin, TX
  • ADMS: Mixed-Signal SoC Design and Verification Workshophttp://www.mentor.com/products/ic_nanometer_design/events/adms_mixed_signal_workshop Aug 7, 2012 : Fremont, CA
  • ADMS: Mixed-Signal SoC Design and Verification Workshophttp://www.mentor.com/products/ic_nanometer_design/events/adms_mixed_signal_workshop Nov 8, 2012 : Fremont, CA

Maximizing Productivity in Advanced SoC and Custom Design Flows with Calibre Integrations

  • Maximizing Productivity in Advanced SoC and Custom Design Flows with Calibre Integrationshttp://www.mentor.com/products/ic_nanometer_design/events/maximizing-productivity-in-advanced-soc-and-custom-design-flows-with-calibre-integrations Jun 5, 2012 : DAC Luncheon

Maximizing Productivity in Advanced SoC and Custom Design Flows with Calibre Integrations

  • Maximizing Productivity in Advanced SoC and Custom Design Flows with Calibre Integrationshttp://www.mentor.com/events/design-automation-conference/networking/maximizing-productivity-in-advanced-soc-and-custom-design-flows-with-calibre-integrations Jun 5, 2012 : DAC Luncheon

Mixed-Signal Design Capture and Simulation within Mentor's Custom-IC Flow Workshop

  • Mixed-Signal Design Capture and Simulation within Mentor's Custom-IC Flow Workshophttp://www.mentor.com/products/ic_nanometer_design/events/ic_flow_workshop Jun 19, 2012 : Fremont, CA
  • Mixed-Signal Design Capture and Simulation within Mentor's Custom-IC Flow Workshophttp://www.mentor.com/products/ic_nanometer_design/events/ic_flow_workshop Aug 23, 2012 : Fremont, CA

Calibre Design-to-Silicon Platform Workshop

  • Calibre Design-to-Silicon Platform Workshophttp://www.mentor.com/products/ic_nanometer_design/events/calibre_physical_verification_workshop Jun 21, 2012 : Fremont, CA
  • Calibre Design-to-Silicon Platform Workshophttp://www.mentor.com/products/ic_nanometer_design/events/calibre_physical_verification_workshop Jul 19, 2012 : Fremont, CA