Calibre Design-to-Silicon Platform Workshop
Select a
Hands-on Workshop
| Location | Date | |
|---|---|---|
| San Jose, CA | Dec 9, 2008 | select |
| San Jose, CA | Jan 13, 2009 | select |
Overview
Mentor Graphics' cordially invites you to attend a FREE, "Hands-on" Calibre Design-to-Silicon Technical Workshop. Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing. The platform offers fast and reliable solutions to design rule checking (DRC), design for manufacturing (DFM), full-chip parasitic extraction (xRC), layout vs. schematic (LVS), silicon vs. layout, and electrical rule checking (ERC).
Attend the workshop and see for yourself why Calibre was adopted by industry leaders --Sun, HP, LSI Logic, AMD, and Motorola -- as well as the top foundries: Chartered, TSMC and UMC and fabless companies -- ATI, Lattice, Vitesse, and Broadcom.
Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot.
Who Should Attend
IC Design Engineers who are serious about an in-depth evaluation of the Calibre Design-to-Silicon platform.
What You Will Learn
- Learn how to reduce turnaround time with advanced Calibre debugging capabilities, directly within your design environment
- See the new Calibre DFM offerings
- Learn how to use Calibre Interactive and RVE to execute DFM functions and visualize DFM results
- Discover simple applications of the Calibre DFM operations
- Understand the benefits of hierarchical vs. flat verification
- Use Calibre DRC to address manufacturability issues
- Use Calibre RVE to highlight DRC errors in a layout environment
- Learn the concepts of hierarchical LVS
- Identify and automatically repair planarity issues in low-density regions
- Identify antennas and understand various repair methods
- Learn about Calibre advanced Nanometer Silicon Modeling capabilities to address:
- Parasitic Inductance Extraction for Analog and RF Designs
- Advanced Hierarchical parasitic extraction
- Precision parasitic extraction for Electromigration and IR Drop analysis