Calibre Design-to-Silicon Platform Workshop
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon (D2S) platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
The Calibre D2S platform offers fast and reliable solutions to design rule checking (DRC), design for manufacturing (DFM), full-chip parasitic extraction (xRC), layout vs. schematic (LVS), silicon vs. layout, and electrical rule checking (ERC).
Seating is VERY limited to maximize your learning experience, submit your interest immediately to request your spot.
Attend the workshop and see for yourself why Calibre is adopted by industry leaders: Sun, HP, LSI Logic, AMD, and Motorola -- as well as the top foundries: Chartered, TSMC and UMC and fabless companies -- ATI, Lattice, Vitesse, and Broadcom.
Who Should Attend
IC Design Engineers who are serious about an in-depth evaluation of the Calibre Design-to-Silicon platform.
What you Will Learn
- Reduce turnaround time with advanced Calibre scaling algorithms and debugging capabilities that directly works within your design environment
- Execute DFM functions and visualize results using Calibre Interactive and RVE
- Understand the benefits of hierarchical vs. flat verification
- Highlight DRC errors in a layout environment by using Calibre RVE Learn the concepts of Waivers and hierarchical LVS
- Identify and automatically repair planarity issues in low-density regions Identify antennas and understand various repair methods
- Use Calibre's advanced Nanometer Silicon Modeling capabilities and understand advanced hierarchical parasitic extraction
- Address manufacturability issues by using Calibre DFM tools that help analyze Critical Areas and features
- Understand the importance of identifying LPC hotspots on advanced design nodes
Advanced Filling Techniques for N20 and Beyond – SmartFill at TSMC
TSMC and Mentor Graphics have a long-standing collaboration in deploying key DFM technologies that meet the ever-changing requirements at advanced nodes. This paper describes the fill challenges faced by...
Foundry Solutions Video Blog: TSMC OIP Conference
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described...
Aerial Image Retargeting (AIR): Achieving Litho-Friendly Designs
In this work, we present a new technique to detect non-Litho-Friendly design areas based on their Aerial Image signature. The aerial image is calculated for the litho target (pre-OPC). This is followed...