Calibre Design-to-Silicon Platform Workshop
Jun 13, 2013
Jul 11, 2013
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon (D2S) platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
The Calibre D2S platform offers fast and reliable solutions to design rule checking (DRC), design for manufacturing (DFM), full-chip parasitic extraction (xRC), layout vs. schematic (LVS), silicon vs. layout, and electrical rule checking (ERC).
Seating is VERY limited to maximize your learning experience, submit your interest immediately to request your spot.
Who Should Attend
IC Design Engineers who are serious about an in-depth evaluation of the Calibre Design-to-Silicon platform.
What you Will Learn
- Reduce turnaround time with advanced Calibre scaling algorithms and debugging capabilities that directly works within your design environment
- Execute DFM functions and visualize results using Calibre Interactive and RVE
- Understand the benefits of hierarchical vs. flat verification
- Highlight DRC errors in a layout environment by using Calibre RVE Learn the concepts of Waivers and hierarchical LVS
- Identify and automatically repair planarity issues in low-density regions Identify antennas and understand various repair methods
- Use Calibre's advanced Nanometer Silicon Modeling capabilities and understand advanced hierarchical parasitic extraction
- Address manufacturability issues by using Calibre DFM tools that help analyze Critical Areas and features
- Understand the importance of identifying LPC hotspots on advanced design nodes
Attend the workshop and see for yourself why Calibre is adopted by industry leaders: Sun, HP, LSI Logic, AMD, and Motorola -- as well as the top foundries: Chartered, TSMC and UMC and fabless companies -- ATI, Lattice, Vitesse, and Broadcom.
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