Accelerating Custom IC Implementation: Speed without compromise Online Seminar

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Overview

The layouts of analog, mixed-signal, and custom digital ICs have to be finely tuned to meet strict constraints on performance, area, power, manufacturability, and yield. To achieve these goals, designers have traditionally employed custom layout techniques that maximize their flexibility, but prolong layout times often into the critical path of a tapeout. To further complicate matters, design rules are increasing in number and complexity causing longer verification cycles. And SoCs are only getting larger while project schedules shrink, requiring parallel circuit and layout design across globally dispersed teams. These challenges demand better methodologies that can significantly accelerate layout productivity without compromising quality and flexibility. This video demonstrates how Mentor's IC Station custom layout platform, with its tight integration to schematic capture and Calibre verification, can help you get the layout quality and speed you need, without compromise.

What You Will Learn

Topics covered:

  • Schematic-driven layout
  • Interactive custom routing
  • High speed automatic routing
  • Physical verification
  • Parasitic extraction and back-annotation
  • Post-layout simulation and analysis

Tools demonstrated:

  • ICstation SDL
    • Parameterized layout device generation based on the source schematic
    • Devices and pin placement and optimization
  • ICAssemble IRoute
    • Connectivity-based interactive routing
    • On-the-fly DRC-aware routing
    • Pushing and sliding of routes
  • ICAssemble ARoute
    • High speed, connectivity-based DRC-aware auto routing
    • Constraint-driven, net-class-based routing
  • Calibre Verification
    • Inline DRC for full/area-based DRC checking, integrated into layout window
    • Inline LVS run and debugging integrated into layout window
    • Calibre xRC parasitic DSPF netlist extraction with schematic-based names and hierarchy
  • Eldo for post-layout simulation
  • Design Architect-IC, ICstation and Calibre RVE for post-layout parasitic analysis
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