Design to Silicon into the 3rd Dimension

Agenda

• 0845 Registration and breakfast
• 0930 Welcome
• 0940 Keynote: Dual Paths Down The Cost Curve: Scaling and 3D
  Joe Sawicki, Vice President and General Manager Design-to-Silicon Division

  Abstract

  For the first time since the first planar integrated circuit was created at Fairchild Semiconductor in 1960, IC and system designers are faced with alternatives to reducing the cost and size, and increasing the performance of electronics products. For 50 years the natural choice was to pack more transistors on a silicon die by making transistors and interconnects smaller. While CMOS scaling appears feasible at least down to the 11nm node, both the design and manufacturing costs associated with further shrinking are high. Designers are now looking seriously at various forms of die stacking—so called “three dimensional” ICs—as an alternative to maintain improving size, power, performance, and cost curves. Mr. Sawicki will discuss the motivations and challenges associated with these two paths, scaling vs. 3D IC. What are the design and manufacturing tradeoffs? Does 3D IC change the design and manufacturing flow? Do designers need new tools and methodologies? How is the semiconductor ecosystem responding? Mr. Sawicki will provide his insight on these and other important questions.

• 1030 AMS Simulation and Custom IC Design Product Vision and Roadmap

  Abstract

  Steve Collis - Technical Director - Analog Design & Verification
  Mentor's product vision, and in depth discussion of analogue mixed signal simulation and custom IC Design Flow tools. Including an introduction to the new custom analog router (to be announced at DAC) and concurrent editing features which SAFELY support multiple designers simultaneously editing within a single cell.

  The session will conclude with a discussion of Mentor’s long term roadmap and strategic technical direction for AMS and customer IC design.

• 1115 Break
• 1130 Olympus SoC: Advanced Solutions for Todays P&R Challenges
  Case study designs – presented by Sondrel

  Abstract

  Itamar Tsachi – Principle P&R specialist

  With each new generation of ICs, challenges emerge as extremely disruptive discontinuities. These major discontinuities can derail the expected benefits of moving to new process nodes and IC architectures. At 28nm and below there are four key discontinuities that have evolved for physical design implementation:

  1) Lithography variations - 193 nm light cannot print 45 nm and smaller patterns without significant distortion. The result is that OPC, CAA and manufacturing effects have to be considered during the design implementation phase.
  
  2) Process and design variations - The number of cell and interconnect variations, design constraints, library and operational modes that need to be considered during physical design threaten yield, performance, reliability, and predictable design cycles.
  
  3) Low power - Low power is a challenge from architecture, through RTL optimization, to physical implementation and verification. Different techniques for power optimization need to be considered.
  
  4) Capacity and runtime - The number of gates in a typical IC has quadrupled since the 180nm node. Designers divide the design into smaller parts to handle the increased size but in doing so schedules slip, engineering costs increase and full-chip closure is far from straight forward.

  This session will discuss the discontinuities facing physical design at advanced process nodes and how Olympus SoC addresses the design challenges.

  Case study designs
  The Olympus SoC presentation will be complemented with detail provided by case studies from industry designs completed by Sondrel.

• 1215 Lunch
• 1345 Design and Manufacturing Co-Optimization
  • Advanced DRC: Getting designs to market faster
  • New Approaches to Circuit Reliability
  • Calibre DFM: A complete offering for stand-alone sign off solutions and also as one integrated to the design flows
  • Calibre InRoute

  Abstract

  Olivier Toublan - Technical Director - IC Verification & Manufacturing Solutions
  Gil Goldbaum - European Applications Engineer - IC Solutions
  Uri Krispil - European Applications Engineer - IC Solutions

  (1) Advanced DRC: Getting designs to market faster This presentation will explore advanced DRC capabilities within the Calibre Platform including: waiver flow, pattern matching, equation based DRC and “real-time” DRC and DfM for digital and mixed signal designs in addition to other DRC/LVS updates. Automatic Waivers: Designs typically include IP or memory that fails strict DRC’s but is still manufacturable and has been given a “waiver” by agreement between the IP creator and foundry/fab. The Calibre nmRC Auto-Waiver flow eliminate re-verifying DRC violations for IP that is good. Pattern Matching: simplifies design rule checks and improves designer productivity with graphical specification of design rules. Equation-based DRC (eqDRC) language provides designers and foundries a way to characterize and evaluate complex multi-variate checks. Calibre® RealTime enables signoff-quality Calibre design rule check¬ing (DRC) in the layout editing environment for custom and analog/mixed-signal design flow. A real time PV flow improves both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.
  
  (2) New Approaches to Circuit Reliability: Implementing a robust verification methodology that addresses circuit reliability is increasingly difficulty. New devices such as thin oxide transistors are less robust to electrical failure and the increasing use of mixed-signal and multi-voltage design techniques increases the likelihood that transistors could be implemented in an incorrect voltage domain. Preventing electrical failure means IC designers should utilize new techniques to validate ESD structures, designs that cross multiple power domains, and sensitive analog circuits. This session describes those challenges and how Calibre PERC addresses these problems.
  
  (3) Calibre DFM: DFM is now a known necessity for advanced nodes. A lot happened in the last year and new features and products moved to the sign-off design flow. Many foundries have made DFM mandatory and some customers are using DFM as a competitive advantage. 20nm is around the corner and the Calibre DFM team has been busy addressing the new challenges to insure design ramp-up at all advanced nodes.
  
  (4) Calibre InRoute: Enables designers to natively invoke Calibre tools within the Olympus-SoC™ place and route system to achieve true manufacturing closure during physical design. Automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity. Improves design quality, eliminates late-stage surprises, and significantly reduces time to closure.

• 1515 Break
• 1530 Tessent Support for 3D IC Testing

  Abstract

  Peter Shields - Euro Applications Engineer - DFT Solutions
  

  • Achieving known-good-die (KGD) to ensure high package yield
  • 3D DFT architecture to provide test access to die within stack
  • Hierarchical ATPG flow applied to testing logic to logic TSVs
  • External Memory BIST for testing logic to memory TSVs
• 1615 Wrap up