DAC Lunch & Learn: Partnering for DFM Compliant IP Seminar

Seminar

There are currently no dates scheduled for this event.

Overview

12 noon—1:30pm

Smart phones. Netbooks, GPS. Digital TVs. Computer graphics cards. These are some of the key applications driving design and tape-out at 65nm and below. These applications are highly cost-driven, and hitting a specific market window may dictate whether the product will be a boom or a bust. Designs must be optimized to have the best chance for highest yields from their foundries. When those designs rely heavily on external IP, customers expect and demand that the IP has been optimized with the latest design-for-manufacturing (DFM) technologies to minimize variability and ensure manufacturability.

This year at DAC, Mentor Graphics, Chartered and ARM are working together to provide a unique perspective on optimizing third-party IP DFM robustness. This partnership has resulted in successful IP DFM compliance since 65nm to the current 32/28nm processes. Topics covered during this presentation will include:

  • Components of Chartered/Common Platform IP DFM solution – flows, tools, acceptance criteria.
  • Benefits of IP DFM from foundry perspective.
  • How DFM is used in the development of ARM IP, both the physical libraries and for their ARM processors.
  • Overview of the Calibre DFM platform and how each of its capabilities are used in the Common Platform DFM flow.
  • PLUS, you'll also have the opportunity to ask your own questions in an exclusive Q&A session.

Seating is limited so submit your interest quickly to reserve your spot.

What You Will Learn

  • How to achieve robust SoC designs with optimized IP by implementing DFM into tools and flows

Presenter Image David Abercrombie

David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last four years at Mentor he has been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. Previously, he has 15 years of experience driving yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. He has also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. He is extensively published in papers and patents on semiconductor processing and yield enhancement. He received his BSEE from Clemson University in 1987 and his MSEE from North Carolina State University in 1988.

Presenter Image Kuang-Kuo Lin

Kuang-Kuo “KK” Lin is a senior manager in the design enablement alliances division at Chartered with responsibility for design for manufacturing (DFM) since 2006.

View Full Bio

Prior to Chartered, KK held engineering and management positions at Intel, Cadence and HP. At Intel, Dr. Lin was involved in leading and driving teams in computer-aided design (CAD), physical design and tape-out operations for 130nm, 90nm, 65nm and 45nm microprocessor products. Dr. Lin has considerable experience in design and process development including DFM, tapeout flows, layout migration/compaction, custom layouts, full-chip integration/planning/place and route, and technology CAD (TCAD). Dr. Lin has published numerous technical articles and presented at many technology conferences. He has received his B.S., M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California at Berkeley.

Presenter Image Rob Aitken

Rob Aitken is an R&D Fellow at ARM. His areas of responsibility include low power design, library architecture, and DFx. His group works on advanced technology and has taped out a number of designs at and below 32nm. He has worked extensively on design, test, and variability issues at ARM, Artisan, Agilent and HP. He has published over 70 technical papers, and holds a Ph.D. degree from McGill University in Canada.

Who Should Attend

  • SoC Designers
  • Custom IP Designers
  • Design Managers
  • Sr. Management in Operations and Business Units

Products Covered

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