Calibre - The Touchstone for IC Design
With the rapid adoption of 28nm technology node, design methodologies are changing in the physical verification world. At this lunch seminar you will learn about the new design checking capabilities available with the Calibre platform. For extra credit we will also include a section highlighting what is coming at the 20nm technology node.
Seating is limited so reserve your spot today to learn how Calibre's accuracy, integration and functionality make it the touchstone of the IC ecosystem.
Lunch will be served.
What You Will Learn
- The major trends in advanced Design Rules and data that is driving an explosion in processing requirements at advanced nodes.
- What Mentor is doing with the foundries to minimize PV run times and minimize how many CPUs are needed to verify designs with all the advanced physical checking rules at 65nm, 45/40nm, 32/28nm and 20nm.
- The benefits of Double Patterning - it's not 2 for the price of 1.
- Why you should be using Pattern Matching now that it has gone main stream.
- 2.5D/3D-IC chip stacking, and what you need to understand to verify mixed technology chips.
About the Presenters
Director of Product Marketing, Calibre Physical Verification, Mentor Graphics
As a manager within the Physical Verification product line, Michael White understands what customers need to succeed and how to create a product roadmap to solve those challenges. He works closely with small and large semiconductor companies around the world to understand their challenges and ensure that Calibre will meet their needs, and yours, for years to come.
John Ferguson is the Lead Technical Marketing Engineer for the Calibre product line at Mentor Graphics in Wilsonville, Oregon. He received a BS degree in Physics from McGill University in 1991, an MS in Applied Physics from the University of Massachusetts in 1993, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology in 2000. He has worked extensively in the area of physical design verification.
John will give the 12/4 presentation, in Irvine, CA.
Who Should Attend
- IC Design Engineers who are about to approach their first 28nm Design, or 28nm engineers wanting to understand the PV challenges as they move towards 20nm