DSPF Back-Annotation Flow in Design Architect IC

Launch Video

Overview

This 15 minute, multimedia demo and tutorial shows how IC designers can utilize Design Architect IC (DA_IC) to easily model parasitic capacitance at each phase of the design cycle. For the initial phase of the design, lumped or cross-coupled capacitance can be annotated directly to critical nets in the schematic. Then, using the Model Selector in DA_IC Simulation Mode, the IC designer can select for a simulation the initial schematic model, the schematic model annotated with a Calibre xRC generated DSPF netlist, or a Calibre xRC generated spice netlist model.

What you will learn:

  • How to annotate estimated lumped and cross-coupled capacitance directly to the schematic
  • How to enter Simulation Mode and run an initial simulation in DA_IC
  • How to back-annotate a DSPF netlist to the schematic
  • How to use the Model Selector to select for simulation the schematic model, a schematic model with DSPF or a registered spice netlist

Tools Demonstrated

  • Design Architect IC – DA_IC 
    • Schematic Entry Mode for adding net properties to the schematic 
    • Simulation Mode for running simulations and selecting various models

Who Should Attend

  • IC Design Engineers 
  • CAD Managers 
  • Project Managers 
  • Quality Engineers

 
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