Pre- and Post-Layout Verification of Mixed-Signal ICs with the ICstudio Platform
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This online presentation and demo shows how mixed-signal IC designers can verify their designs throughout the design process (taking parasitic effects into account, both pre- and post-layout) using the ICstudio mixed-signal design environment. In the demo, a design is taken through multiple verification stages, beginning with pre-layout estimation and verification, followed by parasitic-aware layout creation. The design is then verified using extracted parasitic data. The extensive debug and analysis capabilities of this flow are used to show how parasitic effects can be isolated and minimized.What You Will Learn
Topics covered:
- Estimating pre-layout parasitics and including them into the design schematic
- Simulating the design with estimated pre-layout parasitics
- Parasitic reporting during layout creation
- Annotating post-layout parasitics to the design schematic
- Analyzing and debugging parasitic effects from the schematic
Tools demonstrated:
- ICstudio to manage IC design projects and data
- Design Architect-IC to capture schematics and to annotate parasitic data
- IC Station to create layout and report parasitics "on-the-fly"
- Calibre xRC to extract final layout parasitics
- Eldo to simulate pre- and post-layout effects