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Overview
This online seminar covers current IC device and interconnect modeling practices and techniques for analysis in the analog/RF (cell and block), digital (full chip) and on-chip memory domains as well as future trends in IC physical modeling.
Who Should Attend
- IC Engineers and Engineering Managers
- Verification Engineers and Engineering
- Managers HW Engineers and Engineering
- Managers HW/SW Engineers and Engineering Managers
What You Will Learn
- Introduction to a conceptual framework for eDFM
- RF/Analog Extraction
- Analog/RF modeling challenges and solutions
- Strategies to manage process variation
- Memory
- Setting up hierarchical extraction and enabling simulation
- IR drop and electromigration analysis
- ASIC
- Setting up ASIC extraction
- ntegration into design flows
- Reduction overview
