Calibre nmLVS Integrated Design Debug Environment Demonstration
Overview
This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre nmLVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.
What you will learn:
- How to easily track down IC design errors using Calibre nmLVS
- How to identify the locations of these errors in your design environment
- How Calibre interacts with the Cadence Virtuoso design creation environment
- How Calibre nmLVS can improve your productivity by reducing your LVS debugging time
Tools Demonstrated
- Calibre nmLVS to verify your IC design
- Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment
- Calibre Interactive as a launch platform to re-run your verification once the design has been fixed
Who Should Attend
- Layout Designers
- CAD Managers
- Project Managers
- Quality Engineers