Mentor Forum - Calibre Tech Day
Learn how to leverage the superior performance and capacity of the Calibre® design-to-silicon (D2S) platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
The Calibre D2S platform offers fast and reliable solutions to design rule checking (DRC), design for manufacturing (DFM), full-chip parasitic extraction (xRC), layout vs. schematic (LVS), silicon vs. layout, and electrical rule checking (ERC).
The seminar will provide updates, tips’n’tricks and best practises on the use of the Calibre platform:
Calibre Automated Waivers: Technology details and demonstration
When verifying a design, certain rule check violations can be “waived” by the foundry. “Waivers” need to be managed in the results output to preserve them for analysis and validation. Manually inspecting waivers is very time consuming. The session will explains the Calibre Automated Waiver technology and demonstrates how the solution eliminates the time consuming, manual process.
Calibre RealTime allows Calibre DRC to run automatically on the region around a design edit, providing immediate feedback of design rule violations. The complete Calibre rule file is loaded, but “Check Recipes” control which checks are executed. RealTime runs directly from your design tool and the rule-check results are highlighted within the design tool.
This section of the Calibre Tech Day will explain how designers can be more efficient using RealTime on various design styles.
Calibre LVS & RVE: How to simplify sign-off runs
The Calibre LVS & RVE interface allows designers to investigate and debug Calibre nmLVS discrepancies and shorts in the most efficient manner.
Delegates will be exposed to new features, utilities and working methods to simplify the work required to reach final signoff. The presentation will be complemented with a practical demonstration of the combination of Calibre nmLVS RVE and DesignRev.
Who Should Attend
- IC Design engineers who are both current users of the Calibre Design to Silicon platform and those who are serious about an in-depth evaluation of the solutions.
10.10 Calibre Platform: Update and road map
11.00 Calibre Automated Waivers: Technology details and demonstration
14.00 Calibre RealTime
15.00 Calibre LVS & RVE: How to simplify sign-off runs
16.30 Concluding remarks
SEATING IS LIMITED TO MAXIMIZE YOUR LEARNING EXPERIENCE, SUBMIT YOUR INTEREST IMMEDIATELY TO RESERVE YOUR SEAT.
Atmel Uses Calibre to Increase Yield and Reduces Time-to-Market
Calibre helped cut time-to-market by up to 10X and provided significant savings in wasted mask and silicon creation costs.
Debugging non-texted shorts using Calibre RVE
In this video we will learn how to use Calibre RVE to quickly debug non-texted shorts.