Mentor Forum - Calibre Tech Day
Mentor's IC verification and sign-off includes traditional rule-based physical verification plus parasitic extraction, and it also provides new capabilities and automated technologies that help improve yield by enhancing the design itself.
This seminar delivers practical knowledge for the use of the Calibre® platform to make your experience with it as efficient as possible. Presentation lectures will be complemented with problem solving demonstrations to illustrate tips and tricks collated from interactions with Calibre users from around the world.
Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre's innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues.
Learn how to leverage the superior performance and capacity of the Calibre® design-to-silicon (D2S) platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing.
Delegates will be exposed to new features, utilities and working methods to simplify the work required to reach final signoff. The presentation will be complemented with a practical demonstration of the combination of Calibre nmLVS RVE and DesignRev.
SEATING IS LIMITED TO MAXIMIZE YOUR LEARNING EXPERIENCE, SUBMIT YOUR INTEREST IMMEDIATELY TO RESERVE YOUR SEAT.
Who Should Attend
- IC Design engineers who are both current users of the Calibre Design to Silicon platform and those who are serious about an in-depth evaluation of the solutions.
The Calibre Tech Day is a free to attend, technical seminar led by Mentor experts. Register online now to book your place and to mark your diary.
|09:10||Calibre Platform: Beyond Verification|
|09:45||Calibre PERC: High level checks|
|11:00||Calibre RealTime and its integration into the Pyxis custom IC design platform|
|14:00||Calibre nmDRC & nmLVS: Best practices for debugging problems|
|15:30||Calibre DesignREV: Tips and tricks|
|16:45||Concluding remarks + Prize Draw|