IC Nanometer Design Online Events

Design-for-Manufacturing (DFM) requires a close working relationship between a foundry and its EDA partners to ensure that customers can create competitive designs with the highest possible yield. This presentation demonstrates how the partnership between TSMC and Mentor Graphics is improving performance and yield for our mutual customers working at advanced process nodes. You will learn about TSMC's Active Accuracy Assurance (AAA) initiative to improve the application of foundry process data in EDA tools, and how Mentor Graphics is engaged in AAA to deliver robust DFM solutions for designers today.

As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield.

Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance.

In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself.

This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.

At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes. Sawicki discusses new technology acquisitions and developments, product enhancements, and organizational alignment. He also describes how Mentor is driving toward the integration of its industry-leading IC implementation platforms based on a common vision for delivering first-pass silicon success.

Yield has always been an issue, but with the progression of complex, high-performance nanometer designs, acceptable yield has become more difficult to attain. While manufacturers have traditionally handled yield management, more pressure is being placed on designers to adopt methods that help ensure success.

This presentation and demo covers how to maximize yield by: 1) Identifying the causes of design-to-process interactions and determining how these causes influence yield; 2) Analyzing where issues occur in the design and where these issues can be corrected, enabling yield prediction; and 3) Making the necessary changes, both manually and automatically, that optimize yield.

This online demo shows how Calibre PERC can address reliability challenges that arise during the circuit and electrical verification process. Calibre PERC is specifically designed to perform electrostatic discharge (ESD) and multiple power domain checks. It can be used to perform Advanced ERC checks and design guidelines checks. Calibr PERC allows you to customize checks at the schematic level and layout level. 

This presentation is 20 minutes in duration.

View this online presentation and demo to learn more about the evolution of the Calibre Physical Verification Platform. 

This presentation is 30 minutes in duration.

This online seminar covers how you can benefit from the latest in Calibre physical verification and design for manufacturing technologies. From a history of DRC and LVS to upcoming trends DFM and nanometer silicon modeling, this seminar will show viewers how the Calibre tool suite is continuing to lead the way.

This seminar also discusses the evolution of the Calibre engine and how our integration with all major 3rd party database formats enables design innovation.

This 15 minute, multimedia demo and tutorial shows how IC designers can utilize Design Architect IC (DA_IC) to easily model parasitic capacitance at each phase of the design cycle. For the initial phase of the design, lumped or cross-coupled capacitance can be annotated directly to critical nets in the schematic. Then, using the Model Selector in DA_IC Simulation Mode, the IC designer can select for a simulation the initial schematic model, the schematic model annotated with a Calibre xRC generated DSPF netlist, or a Calibre xRC generated spice netlist model.

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