Olympus-SoC Place and Route Solution for Advanced Nodes

There are currently no dates scheduled for this event.

Overview

With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs, but at the same time they are faced with a variety of design challenges that significantly impact project cycle time and quality of results. Key challenges such as larger design size, stringent low power requirements, multi-mode multi-corner timing, power and SI closure, and lower yield due to manufacturing variations have a major impact on performance and productivity.

In this session we will give an overview of the Olympus-SoC place and route system and how it effectively addresses these challenges. We will describe new capabilities, including enhancements to MCMM design closure, distributed optimization for faster throughput, new techniques in gdsii-to-gdsii flow, timing aware automatic fast macro placement, and low power design enhancements. We will also introduce Calibre InRoute, Mentor's new manufacturing closure solution that provides Calibre DRC/DFM closure inside Olympus-SoC.

Seating is limited so submit your interest quickly to reserve your spot.

What You Will Learn

• Advanced capabilities of the Olympus P&R system to handle advanced node design challenges.
• Design closure with Multi-Corner Multi-Mode based concurrent timing, SI and Power optimization
• UPF based low power implementation including advanced MVDD flow and low power CTS
• Sign-off physical verification (DRC/LVS/DFM) during implementation with Calibre InRoute
• Advanced chip assembly flow for handling big designs