Revolutionizing DRC: Calibre nmDRC

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Overview

At 90 nm and below, the dramatic increase in the number and complexity of DRC rules is taking a toll on DRC cycle time: from first-pass through tape-out clean. Mentor Graphics has a solution - Calibre nmDRC. Please view and learn more about the revolutionary changes that transformed Calibre DRC into Calibre nmDRC.

Who Should Attend

IC Design and CAD Engineers and Managers looking to reduce DRC Cycle Time and improve Time to Market

What You Will Learn

  • DEMO: Reducing DRC Runtime Through Scaling
  • How Calibre's new TCL based TVF syntax simplifies the complexities of supporting complex rule files
  • How Calibre's Hyperscaling processing engine has been expanded to offer significant scaling, dramatically reducing DRC runtimes at the full-chip level
  • What Mentor is doing to dramatically reduce debug and iteration time with the next generation of Calibre RVE
  • How to dramatically reduce debug time by viewing and debugging errors dynamically, while the DRC job is processing.
  • How to substantially cut iteration time through automatic incremental re-verification
  • What Calibre is doing to continue to address physical verification challenges in the future
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