Tower Success Story: The Calibre xRC Hierarchical Flow

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Overview

The ever-increasing demand for more performance from IC design poses challenging requirements on the parasitic extraction tools and their usage. Low-voltage high-speed designs emphasize parasitic devices that need to be modeled and simulated accurately.

This presentation, given at the 2005 User2User conference describes how a foundry (Tower Semiconductor LTD.) builds an accurate Calibre runset for extraction and how a designer can use such a runset to achieve front-end designs from a block level to a full chip.

Who Should Attend

  • Circuit designers who create embedded memory, RAM, processors and mixed-signal ICs
  • Foundry Managers
  • Operations Managers
  • Project Managers
  • Quality Engineers

What You Will Learn

  • Creating parasitic runsets for xRC
  • Runset testing/QA
  • Comparing extraction vs. silicon data
  • Flat/hierarchy extraction results
  • Block-level and full-chip extraction data
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