A primary concern for most circuit designers is achieving simulation results that are accurate with respect to silicon measurements.
This is increasingly important at smaller process nodes and is not restricted to just timing simulation but also power, signal integrity, crosstalk, electromigration and many other analysis concerns.
The simulation accuracy can only be good as the silicon model that is created by device and parasitic extraction tools. Calibre LVS, xRC, and xL work in conjunction to provide a comprehensive silicon model that has field-solver like accuracy as well as incorporating physical effects such as in-die variation, copper loss, and impact of metal fill that is suitable for accurate downstream analysis tasks.
This interface provide users with the capabililty to access data in industry standard formats (GDS, spice netlists) from the SVDB directory after a Calibre LVS-H run
IC Device and Interconnect Extraction for Analysis
This online seminar covers current IC device and interconnect modeling practices and techniques for analysis in the analog/RF (cell and block),
digital (full chip) and on-chip memory domains as well as future trendsin IC physical modeling.
