Calibre xRC

  • Delivers unparalleled performance on ASIC, memory, analog, SoC designs, etc. with no trade-off in accuracy
  • Single rule file can drive DRC, LVS, and Calibre xRC functionality
  • Reads LVS data structures to integrate parasitic information with intentional circuit elements
  • Model-based engine calculates intrinsic and coupling capacitances for all nets using the same high degree of accuracy
  • Integrates with Calibre DRC and LVS, Calibre Interactive, Calibre View and Calibre RVE, which offer powerful verification and cross-probing capabilities

Benefits:

  • Extraction and simulation results correlate closely with silicon measurements
  • Offers AMS SoC designers a single parasitic extraction solution that is independent of design style or flow

Online Event

IC Device and Interconnect Extraction for Analysis
This online seminar covers current IC device and interconnect modeling practices and techniques for analysis in the analog/RF (cell and block), digital (full chip) and on-chip memory domains as well as future trends in IC physical modeling.

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