Mentor.com :: IC Design Resources

News Article:Fujitsu Semiconductor Expands Use of Calibre for Advanced IC Physical Verification and Design for Manufacturing

Mon, 23 Jan 2012 14:00:00 GMT

WILSONVILLE, Ore., January 12, 2012 — Mentor Graphics Corp. (NASDAQ: MENT) today announced it has signed a preferred, long-term partnership agreement with Freescale Semiconductor to deliver state-of-the-art, high-speed simulation platforms for Freescale’s QorIQ® P-Series, AMP and QorIQ Qonverge™ product lines of multicore embedded processors. In support of this partnership, Mentor® now offers a powerful virtual prototyping environment and enabling technologies which allow Freescale customers to achieve early, more efficient software integration and accelerate their product delivery cycles.

White Paper:Modern IC Packaging

Mon, 23 Jan 2012 08:00:00 GMT

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies.

White Paper: Ready for 3D-IC

Thu, 19 Jan 2012 08:00:00 GMT

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.

White Paper:3D-IC System Verification Methodology: Solutions and Challenges

Thu, 19 Jan 2012 08:00:00 GMT

Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates a true 3D-IC stack verification using a GDS based flow.

White Paper:Analyzing the Device Parasitics Sensitivity and Accuracy of Calibre xACT 3D Field Solver Extraction

Tue, 03 Jan 2012 08:00:00 GMT

As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and accuracy specifications. Mentor’s new parasitic extraction tool, Calibre® xACT 3D, enabled the Semiconductor Technology Academic Research Center (STARC) to easily and accurately extract the capacitance adjacent to a device on an individual component basis, and create a new reference based on the extraction. With its unique technology and high-quality performance, Calibre xACT 3D can be an integral part of the sophisticated extraction flow needed for today’s complex designs and advanced process technologies.

Product Demo:Pyxis TFT / Flat Panel Display Solutions

Wed, 30 Nov 2011 14:00:00 GMT

In this presentation and demonstration you will see some of the features/functions available with Mentor's Pyxis Custom IC Design solutions that address the unique challenges of TFT/Flat Panel design.

White Paper:Describing PERC-based Intent Driven Design

Mon, 21 Nov 2011 08:00:00 GMT

In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout level.

White Paper:How to Reduce the Need for Guardbanding a Flash ADC Design

Thu, 17 Nov 2011 08:00:00 GMT

For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding and ensures that it will work according to the specifications when manufactured.

News Article:Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement

Fri, 11 Nov 2011 14:00:00 GMT

WILSONVILLE, Ore., November 11, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced it was chosen as a TSMC 2011 Partner of the Year for its role in 3D-IC design enablement. The Mentor® and TSMC collaborations provide a robust flow for verifying multi-die system designs using silicon interposer integration techniques.

News Article:Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System

Fri, 04 Nov 2011 13:00:00 GMT

WILSONVILLE, Ore., November 4, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced the successful tapeout of a 20 nm test chip in collaboration with STMicroelectronics, marking a significant milestone in the development of a complete Mentor® design-to-silicon solution for next-generation process technology. The test chip was implemented using the Olympus-SoC™ place and route system, and verified using the Calibre® nmDRC platform, which is the verification and double patterning solution used by R&D teams at STMicroelectronics. Together, the Olympus-SoC, Calibre and Tessent® silicon test and yield analysis products provide a comprehensive flow for 20 nm IC development.