Mentor.com :: IC Design Resources

Technology Overview:How to automatically replace LEF abstracts with GDS IP

Thu, 13 Jun 2013 07:00:00 GMT

How to automatically replace LEF abstracts with GDS IP in Calibre Physical Verification for LEF/DEF input Overview: Physical Verification or other downstream analysis flow of P&R design data which only includes routing layers can miss issues caused by the current device level IP which is only represented by LEF abstracts. However, replacing the LEF IP abstracts with the current GDS version provided by layout teams can easily be merged with the DEF routing information and output to disk or in memory during Calibre Physical verification.

This video steps through an example showing how to run this Calibre utility to merge the GDS data with DEF.

Review inputs for reading LEF/DEF
Convert LEF/DEF routing data to GDS on disk
Replace LEF abstracts with GDS IP during DEF conversion

News Article:SilabTech’s 28nm High-Speed PHYs Delivered Ahead of Schedule with Mentor Graphics Tool Flow

Mon, 10 Jun 2013 02:30:00 GMT

WILSONVILLE, Ore., June 9, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced that SilabTech Pvt. Ltd. has achieved first silicon success for their latest 28nm high-speed, mixed-signal PHY IPs for PCI Express, SATA, MIPI, M-PHY and USB 3.0 in advance of the planned schedule.

Technology Overview:How to edit in place from top-level in Calibre DESIGNrev

Thu, 06 Jun 2013 07:00:00 GMT

This video will demonstrate how to edit the polygons at certain instances of the design from the top-level in order to fix some DRC violations.

News Article:Mentor Graphics to Provide Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM for Freescale

Tue, 04 Jun 2013 13:00:00 GMT

WILSONVILLE, Ore., June 4, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced that Freescale® Semiconductor (NYSE:FSL, FSL.B) has selected Mentor as an ideal partner in the silicon test, yield analysis, physical verification and DFM technology areas.

Success Story:Dukosi

Mon, 03 Jun 2013 07:00:00 GMT

Eldo and Pyxis ensure coverage of expected spread and achievement of parametric yield targets: Superior design rule checking; Using Calibre’s foundry gold standard design rules removes uncertainty and shaves one.

Success Story:On Semiconductor

Mon, 03 Jun 2013 07:00:00 GMT

On Semiconductor's automotive products division, located in East Greenwich, Rhode Island, has completed multiple successful tape outs using the Pyxis® Custom IC Router, including a highly integrated, complex power chip.

Success Story:ASO

Mon, 03 Jun 2013 07:00:00 GMT

Eldo Premier transient noise analysis feature achieves both accuracy and performance when simulating large scale analog/ mixed signal circuits for flicker noise effects.

Success Story:Japanese Advanced Automotive Technology

Sun, 02 Jun 2013 07:00:00 GMT

A world-leading, Japanese supplier of advanced automotive technology, systems, and components needed an analog mixed signal simulator that provided full, transistor-level SPICE accuracy at faster simulation speeds than what they were using at the time. Because Eldo® Classic was their golden reference SPICE simulator, they wanted to evaluate Eldo Premier to verify the speedup factor it could obtain for their big simulations.

News Article:Mentor Graphics and Samsung Optimize 14nm Process Design Kits

Fri, 31 May 2013 20:00:00 GMT

WILSONVILLE, Ore., May 31, 2013—Mentor Graphics Corp. (NASDAQ: MENT today announced that Calibre® nmDRC™ and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release.

News Article:Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement

Thu, 30 May 2013 20:00:00 GMT

WILSONVILLE, Ore., May 30, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC™ netlist-to-GDS platform.