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A Complete, Integrated IC Design Environment

To help companies jump-start their design cycles and cut time-to-market, Mentor Graphics and its foundry partners have developed IC design kits, which include all the foundry-specific data files and models for use with the Mentor Graphics front- and back-end IC design tools. Available from major foundries, these kits enable the entire design workflow to be supported by foundry-specific processes

The design kits contain customizable, easily expandable building blocks for schematic capture, simulation, physical layout, and verification, which allow you to create a complete, integrated IC design environment that’s tailored to the foundry process technology for your design.

Mentor Graphic’s Custom IC flow and its integrated schematic, extraction and simulation tools allow you to take a design from system specifications to post-layout verification with a virtually seamless approach.

PDK Portfolio

Foundry 0.6+ 0.5 0.35 0.25 0.18 0.13 90nm 65nm 55nm 45/40nm 28nm 16nm
Atmel AT56000High-V
Austria Microsystems  
  • 0.35 CMOS (C35)*
  • 0.35 SiGe-BiCMOS (S35)*
  • 0.35 HV-CMOS (H35)*
  • C35 B4S3
  • C35 B3S3
  • H35 B3S1
  • S35
Dongbu
  • BA350*
  • BD350BA
  • BD18BB
  • BD180_LV
  • AN180
GLOBALFOUNDRIES 035MMRF S/G*
  • 0.18MMRF*
  • .18ULL HV*
  • .18ULL HV
  • .13LP*
  • .13RFLP
  • .13RFLP*
  • .13 BCDLite
90G*
  • 65LP*
  • 65G*
       
Grace        
  • HV H018S6LB
  • GF013Q7PR
  • MM A013S7G0
           
HHNEC     BCD350GE                  
IBM
  • 5HP*
  • 5DM*
  • 7HP*
  • 7WL*
  • 7RF
  • 7RF (ML/AM)*
  • 8RF
  • 8RF*
  • 7HV
  • 9SF
10SF
L Foundry LF150
MagnaChip HL35S
  • HL18GF
  • HL18E40
  • 18E50GF
On Semi C5 BiCMOS*
  • C035M
  • C3D3
  • I3T50/80*
  • D3N
Polar Semi PBC4*
Peregrine 0.25/0.50 RF* 0.25/0.50 RF*
Silterra
  • 0.18MMRF*
  • CL180MR
SMIC
  • 0.18MMRF*
  • .18EEPROM*
  • 0.13MMRF*
  • 0.13MMRF
65LL
TowerJazz
  • SBC35 SiGe*
  • BC35 BiCMOS*
  • TS35PM
  • SBC35
  • TS35PM iPDK
BCD25*
  • SBC18 SiGe*
  • CA18HR CMOS*
  • TS18SL/PM*
  • TS018 iPDK
  • TS18RF
  • SBC18 hx
  • CA18HD
  • TS18sl iPDK
  • TS18PM iPDK
TS13SL*
TSMC
  • 035MM*
  • 0.35 Logic*
  • 025MM3.3V*
  • 025MM5.0v *
  • CL018G Logic*
  • CR018G RF*
  • SG018 SiGe*
  • CM018G*
  • CR180GPII
  • CR180GMMRF
  • CE018
  • CR180GPII
  • CR180GPII iPDK
  • CL013G*
  • CM013RG*
  • CL013LP*
  • CL013LV*
  • CR013G iPDK
  • CMN90MG*
  • CMN90MP*
  • CLN9G*
  • CRN90LP
  • CRN90LP iPDK
  • CL65G*
  • CL65GP*
  • CRN65GP*
  • CRN65LP*
  • CRN65LP iPDK
  • CRN65GP iPDK
  • CRN55LP iPDK
  • CLN45GS*
  • CLN40LP*
  • CRN40LP*
  • CRN40LP iPDK
  • CRN40G iPDK
  • CLN28HPL iPDK
  • CRN28HPL iPDK
  • CRN28HP iPDK
  • CLN28LP iPDK
  • CLN28HPM iPDK
  • CLN28HP iPDK
  • CRN28HPM iPDK
  • CRN28LPP iPDK
  • CLN28HPC iPDK
CLN16FF iPDK
VIS 0.5um HV*
UMC
  • 0.35 CDMOS
  • 0.3 BCD
  • 0.3 HV
0.25MMRF*
  • 0.18MMRF*
  • 180LGII Logic*
  • 0.18 CDMOS
  • 0.18 CDMOS*
  • 0.18LL MM*
  • 0.18 CIS
  • 0.18 EFLASH
  • 0.18 MMRF
  • 0.13MMRF
  • 0.13MMRF*
  • 0.11 MMRF AEs
  • 90nm MMRF*
  • 90nm MMRF
65nmSP .55LP
X-Fab
  • XC06*
  • XC06
  • XB06*
  • XT06*
  • XHB06*
  • XHB06
  • XDM10*
  • XDH10*
  • XH035*
  • XH035
  • XA035*
  • XA035
  • XO035*
  • XU035 (A)
  • XH018*
  • XH018
  • XT018* (A)
  • XT018 (A)
  • XC018*


* v2008.x Kit, will need to be re-qualified for v9/v10.

PDK Components

  • Pre-configured symbols for schematic capture, with predefined properties for Eldo simulation, schematic-driven layout with IC Station®, and Calibre LVS
  • Pre-configured process definition file for IC layout
  • Foundry-supported Calibre® DRC and LVS rule files
  • Foundry-supported Eldo® models
  • Pre-configured netlist configuration file
  • Programmable device generators for each component that produce correct-by-construction layouts in IC Station directly from schematic symbols
  • Userware to customize the library palettes listing the available components

PDK Benefits

  • Ensures manufacturing success
  • Speeds the setup of complete schematic and layout design environments
  • Reduces costly rework cycles due to DRC/LVS errors with correct-by-construction device generators
  • Eliminates expensive mistakes due to inaccurate simulation models
  • Available at no cost to customers

PDK Documentation

  • Release_notes: Unique requirements for the PDK and revision history. This file documents which specific Eldo models and DRC/LVS files were used to validate the design kit.
  • Installation_Guide: Brief description of PDK contents and installation procedure.
  • Library_Specification.pdf: List of Components included in the PDK describing the menu name and associated model names and properties.
  • Users_Guide.pdf: Users guide and tutorial.

To request a design kit, please contact your local Mentor Graphics account representative. If you are not currently working with a Mentor representative, please contact Mary Rayburn.

 
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