Layout Verification


Calibre DRC and Calibre LVS are the market share leaders in physical verification. Its high scaling hierarchical processing delivers the fastest turn around times in the industry.

Calibre's adoption as the sign-off standard at all of the top foundries ensures accurate results for first time success tape-outs. With integrations to all the industry leading physical design creation tools, Calibre's Results

Viewing Environment (RVE) reduces the length times required in debugging complex issues like shorts, antennas and density from days or hours to minutes. Together, these and the other benefits of Calibre ensure the fastest cycle time through physical verification to tape out, and ultimately working silicon.


  • Olympus SoC

    The Olympus-SoC solution delivers innovative technologies for 65 and 45 nm processes. It provides the next-generation place and route system that concurrently addresses variations in lithography, process corners, and design modes. Integral to Olympus-SoC is Mentor’s detailed routing architecture which embeds variation-aware timing, optimization and litho-modeling to address optical proximity correction (OPC) and resolution enhancement technology (RET) effects early in the design cycle ensuring faster timing closure for complex process rules. It is capable of simultaneously solving for dozens of different process corners and design modes, ensuring an optimized chip without unnecessary guard banding.

  • Pinnacle

    The Pinnacle suite provides the fastest and the best design for variability implementation solution for the biggest chips. Built on revolutionary platform architecture Pinnacle delivers the best performance Design for Variability (DFV) engine, handles extremely large designs, and plugs seamlessly into existing design flows. Rapid Physical Feasibility features help engineers in the early design phase to refine and finalize the floor plan and respond to complex design constraints.

  • Calibre nmDRC

    The industry standard for design rule checking.

  • Calibre LVS

    Industry standard physical verification tool for layout versus schematic.

  • Calibre YieldAnalyzer

    Integrated suite of analysis tools to reduce variability in design-related yield loss

  • Calibre YieldEnhancer

    Layout modification platform to automate design yield enhancement

  • Calibre RVE

    Calibre RVE gives designers a tool that is easy to use and gives the information they need to quickly repair errors.

  • Calibre Interactive

    This interface provide users with the capabililty to access data in industry standard formats (GDS, spice netlists) from the SVDB directory after a Calibre LVS-H run.

Events

AAA and Advanced DFM—Collaboration for Success
Design-for-Manufacturing (DFM) requires a close working relationship between a foundry and its EDA partners to ensure that customers can create competitive designs with the highest possible yield.

Approaching Yield in the Nanometer Age: The Framework for an Extensible DFM Methodology
This online tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.

Calibre Design-to-Silicon Platform Workshop
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing

Mentor Technology Viewpoint: DFM
 
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