Olympus: Solution

Next Generation Netlist-to-GDSII System Comprehensively Addresses Variations in Design Modes, Process Corners, and Lithography.

With early 65nm chips heading towards production and 45nm test chip trials under-way, three critical physical design tool needs have emerged: lithography-aware physical implementation; variation-based timing closure; and capacity to handle extremely high gate counts.

Litho-Aware Implementation

At 65nm process nodes and below, one of the biggest factors affecting yield is design and process variations. There is increasing distortion in the printed patterns vis-à-vis the intended structures in the layout database. This problem manifests itself in the form of manufacturing faults such as bridging, pinching and via failures. OPC simulation and RET address this challenge. However, at 65nm and 45nm nodes, the number of issues becomes very large, and trying to fix them all in manufacturing becomes intractable. Further, litho-related layout modifications done in isolation of design metrics, such as timing and leakage and other parametrics, can lead to performance degradation and timing-related chip failures.

Design for Variability

Design for Variability (DFV) refers to analysis and implementation of a physical design taking into account multiple design contexts or modes, as well as timing variations due to device and interconnect scaling. Approximations, like merging constraints over design modes or merging process corners, result in significant loss of accuracy, which impacts design yield, timing closure and time-to-market. Designers often must iterate unpredictably in sign-off ECO loops, or add pessimistic margins resulting in designs with larger area and power dissipation, and lower yields.

Built for Scalability

With the rapid growth in design sizes, designers are moving to larger block sizes in hierarchical flows. In addition, designers are using flat physical design flows to reduce die-area and cost. Chip Assembly flows are also gaining traction to achieve top-level design closure over multiple blocks. Designers need very high capacity physical implementation tools to address large designs with a variety of design styles including flat, hierarchical and hybrids.

Current-generation design implementation systems are simply not architected to handle these inherent challenges that arise at 65nm and beyond. Olympus-SoC was purpose-built to provide a highly efficient and scalable analysis architecture that can accommodate an arbitrary number of timing graphs that concurrently represent each variation scenario (and its related set of design corners) in a truly concurrent manner. Olympus-SoC gives designers the ability to optimize designs subject to variations in design modes, as well as lithography and other manufacturing processes windows, in a comprehensive and holistic fashion.