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Calibre RealTime

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Calibre RealTime

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Calibre RealTime

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Compact AC Modeling and Performance Analysis of...

White Paper

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency...

Abstract

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

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Characterizing PLL Jitter from Power Supply Fluctuation...

White Paper

Characterizing PLL Jitter from Power Supply Fluctuation Using Mixed-Signal

Characterizing PLL Jitter is important yet challenging. Usually done through transistor-level transient analysis, slow simulation speed has been the major bottleneck preventing jitter from being characterized...

Abstract

Characterizing PLL Jitter from Power Supply Fluctuation Using Mixed-Signal

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A Nonlinear S-parameters Behavioral Model for RF...

White Paper

A Nonlinear S-parameters Behavioral Model for RF LNAs

A nonlinear behavioral model for radio frequency low noise amplifiers (LNA’s) is presented. The model captures effects of nonlinearity, output power saturation, noise figure and port impedance mismatch....

Abstract

A Nonlinear S-parameters Behavioral Model for RF LNAs

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Advanced Manufacturing Closure with Calibre® InRoute...

White Paper

Advanced Manufacturing Closure with Calibre® InRoute and Olympus-SoC

Achieving manufacturing signoff is getting more difficult at each node as we encounter significant manufacturing limitations and variability. This paper describes the physical signoff challenges seen in...

Abstract

Advanced Manufacturing Closure with Calibre® InRoute and Olympus-SoC

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Combining Low Pin Count Test with Scan Compression...

White Paper

Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost

The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand...

EDT, LPCT

Abstract

Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost

TAGS: EDT, LPCT

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An Optimizer-Assisted Design Methodology For A Two...

White Paper

An Optimizer-Assisted Design Methodology For A Two Stage Wideband Feedback Amplifier

With the increasing design complexity and requirements imposed by the various functionalities of modern SoC’s, the analog design process can become a tedious iterative task that may consume a considerable...

Design Methodology, SoC

Abstract

An Optimizer-Assisted Design Methodology For A Two Stage Wideband Feedback Amplifier

TAGS: Design Methodology, SoC

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Addressing Mixed-Signal SoC Physical Design Challenges

White Paper

Addressing Mixed-Signal SoC Physical Design Challenges

Design teams have adopted the mixed signal simulation flow to address the increased demand for mixed mode functionality on a single chip. The physical design environment could benefit from a similar approach...

Analog Design, Mixed-Signal, SoC

Abstract

Addressing Mixed-Signal SoC Physical Design Challenges

TAGS: Analog Design, Mixed-Signal, SoC

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The Roadmap to LFD Value: Quantifying a Return on...

White Paper

The Roadmap to LFD Value: Quantifying a Return on Investment in Calibre LFD

By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently...

Calibre

Abstract

The Roadmap to LFD Value: Quantifying a Return on Investment in Calibre LFD

TAGS: Calibre

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