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Experience with OVM-Based Mixed-Signal Verification...

White Paper

Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface

Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM.

Abstract

Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface

Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM.

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Thickness-aware LFD for the hotspot detection induced...

White Paper

Thickness-aware LFD for the hotspot detection induced by topology

A methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range encountered due to different topology in different areas...

Abstract

Thickness-aware LFD for the hotspot detection induced by topology

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Pyxis TFT / Flat Panel Display Solutions

Product Demo 10:39

Pyxis TFT / Flat Panel Display Solutions

In this presentation and demonstration you will see some of the features/functions available with Mentor's Pyxis Custom IC Design solutions that address the unique challenges of TFT/Flat Panel design.

flat panel, tft

Abstract

Pyxis TFT / Flat Panel Display Solutions

TAGS: flat panel, tft

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Describing PERC-based Intent Driven Design

White Paper

Describing PERC-based Intent Driven Design

In this paper, we present a fully automated CAD solution that captures the designer’s intent from the schematic netlist, and links these annotations to the proper devices or nets on the physical layout...

Abstract

Describing PERC-based Intent Driven Design

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How to Reduce the Need for Guardbanding a Flash...

White Paper

How to Reduce the Need for Guardbanding a Flash ADC Design

For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits...

Abstract

How to Reduce the Need for Guardbanding a Flash ADC Design

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Escape the tape-out crunch with Pyxis Concurrent

Product Demo 03:49

Escape the tape-out crunch with Pyxis Concurrent

Pyxis Concurrent enables multiple users to edit the same cell at the same time. Instead of placing the chip finishing duties solely in the hands of a single layout engineer, Pyxis Concurrent allows the...

Chip Finishing, Concurrent Editing, Custom Layout, Layout Process, RealTime DRC

Abstract

Escape the tape-out crunch with Pyxis Concurrent

TAGS: Chip Finishing, Concurrent Editing, Custom Layout, Layout Process, RealTime DRC

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Pyxis Custom Router Demonstration

Product Demo 10:28

Pyxis Custom Router Demonstration

Pyxis Custom Router, an add-on option for Pyxis Implement, introduces an integrated tool box of advanced custom routing functionality. The tool box includes a global router for congestion mitigation, a...

Chip Finishing, Concurrent Editing, Custom Layout, Layout Process, RealTime DRC

Abstract

Pyxis Custom Router Demonstration

TAGS: Chip Finishing, Concurrent Editing, Custom Layout, Layout Process, RealTime DRC

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Deep Submicron Solutions - Division Overview

Technology Overview 24:03

Deep Submicron Solutions - Division Overview

The Deep Submicron Division is meeting the needs of complex Analog and Mixed Signal design and verification with dramatic productivity improvements through unique automation plus advanced features to reconcile...

AMS

Abstract

Deep Submicron Solutions - Division Overview

TAGS: AMS

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Routing Technology for Advanced-Node IC Designs

White Paper

Routing Technology for Advanced-Node IC Designs

As the IC industry accelerates towards the adoption of 32nm and 28nm process nodes, designers face significant new challenges with digital routing. These challenges to sub-nanometer routing—including...

Abstract

Routing Technology for Advanced-Node IC Designs

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