Calibre Solutions for Advanced DRC
This three part web seminar will address the latest Calibre solutions for advanced verification:
Part 1: eqDRC – Solutions for Advanced Layout Checking
With the addition of Equation Based DRC (eqDRC), Calibre nmDRC now offers a new approach to defining and implementing complex DRC checks. In addition to simplifying existing checks and enabling checks that could not otherwise be done, Calibre eqDRC provides a generalized modeling environment.
Part 2: gridDRC - Solutions for Restrictive Design Rules
To ensure the manufacturability and performance of chips at 22 nm, many foundries are implementing restrictive design rules (RDR)—limiting the type and placement of features used in designs. Extensive use of pitch and complex grid constructs introduce new physical verification challenges for this type of methodology.
Part 3: PERC – Solutions for Advanced ERC, ESD, and Multi Power Domain Checking
ESD, advanced ERC, and multiple power domains are top issues on a long list of complex new geometrical and electrical verification requirements. Calibre PERC was developed to address these reliability challenges that arise during the circuit and electrical verification process.
What You Will Learn
- How eqDRC enables simple specification of difficult checks, providing greater accuracy and design area reduction
- How eqDRC can improve yield and reliability issues by accurately modeling complex failure mechanisms
- New methods for implementing Restrictive Design Rule checks How to resolve the debug challenges associated with advanced equation based and restrictive design rules
- How Calibre PERC combines the schematic level topology recognition with geometric checks to enable customized ERC checks including ESD and multiple power domains
PLUS you’ll also have the opportunity to ask your own questions in an exclusive live Q&A session
About the Presenter
David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last four years at Mentor he has been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. Previously, he has 15 years of experience driving yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. He has also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. He is extensively published in papers and patents on semiconductor processing and yield enhancement. He received his BSEE from Clemson University in 1987 and his MSEE from North Carolina State University in 1988.
Who Should View
- Design Verification Engineers and Managers
- CAD Engineers and Managers
- Design Rule Definers and Writers
- Anyone working in the physical verification area of design