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Device Noise Analysis of Switched-Capacitor Circuits

Details

Overview

This webinar reviews analysis techniques to accurately analyze the noise performance of switched-capacitor circuits and provides simulation examples using the BDA the Mentor AFS Platform that complement and verify the theoretical treatment.

What You Will Learn

  • Analysis techniques to accurately analyze the noise performance of switched-cap circuits
  • Circuits discussed range from basic passive and active T/H circuits, to integrators, to SC delta-sigma modulators
  • Simulation examples using the BDA the Mentor AFS Platform complement and verify the theoretical treatment
  • Circuits discussed range from basic passive and active T/H circuits, to integrators, to SC delta-sigma modulators.

About the Presenters

David Lee

David Lee is Principal Engineer for the Analog/Mixed-Signal Verification Business Unit at Mentor. Prior to Mentor, David was an Architect at Berkeley Design Automation. He has over 20 years of EDA experience and is well-versed in the art of precision analog/RF circuit simulation. David received his B.A.Sc. and M.A.Sc. degrees in Systems Design Engineering from the University of Waterloo. David has held positions with Northern Telecom, Bell Northern Research, and AT&T Bell Laboratories. David is a Sr. Member of the IEEE.

Boris Murmann

Boris Murmann is an Associate Professor in the Department of Electrical Engineering, Stanford, CA. He received the Ph.D. degree in Electrical Engineering from the University of California at Berkeley in 2003. From 1994 to 1997, he was with Neutron Mikrolektronik, Germany. Dr. Murmann's research interests are in the area of mixed-signal integrated circuit design, with emphasis on data converters and sensor interfaces. Boris is the recipient of various awards and serves in several IEEE committees.

Who Should View

  • IC design engineers that work with switched-capacitors circuits to implement analog functions in CMOS technology.
  • CAD and verification engineers that are interested in analog circuit verification techniques.
 
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