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Calibre Advanced DRC: Avoid the Waiver Productivity Tax with Calibre Auto-Waivers

Overview

The IC industry is moving towards larger SoC designs that incorporate a growing amount of custom and 3rd party IP and embedded memory. Competitive designs typically have some IP or memory that fails strict DRC's but is still manufacturable and has been given a "waiver" by agreement between the IP creator and foundry/fab. Unfortunately, the chip designer often doesn't get the waiver information and wastes hour after hour re-verifying tens of thousands of DRC violations for IP that is good. This is an enormous productivity sink hole that we have now plugged with our new Auto-Waiver flow in Calibre nmDRC.

What You Will Learn

With the increased demands from design rule requirements, considerable time can be wasted redundantly debugging errors which have been considered acceptable, or "waived". This presentation will provide insight into automation within the Calibre physical verification tools to eliminate this redundancy, significantly improving time to market.

About the Presenter

Presenter Image John Ferguson

John Ferguson is the Lead Technical Marketing Engineer for the Calibre product line at Mentor Graphics in Wilsonville, Oregon. He received a BS degree in Physics from McGill University in 1991, an MS in Applied Physics from the University of Massachusetts in 1993, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology in 2000. He has worked extensively in the area of physical design verification.

Who Should View

Layout and physical design engineers for IP design or SoC chip level design as well as CAD engineers and managers looking to improve their physical verification through-put.

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