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Beyond Physical Verification: Advanced Electrical Rule Checking on Layout

Overview

This seminar will present advances in methods and tools to spot those issues, covering the requirements for effectiveness: versatility, user-friendliness, capacity for full-chip verification.

Chips designed at the latest technology nodes are prone to a variety of design errors that may not easily be identified by traditional physical verification tools. Many of these errors can result in electrical failure. Identifying and correcting these errors is critical for designers to produce working silicon.

Traditionally, designers have relied on Electrical Rule Checking (ERC) for this type of verification and most ERC methodologies combine physical verification techniques, simulation and manual checking. As designs incorporate more mixed-signal content, the complexity of checks for issues such as Electrostatic Discharge has increased, and reliance on manual checking and time-consuming simulation becomes problematic.

Schematic-based checks are not sufficient and Chip Designers need new tools that can automate schematic-driven, layout-based ERC checks to eliminate lengthy and error-prone manual checking of the physical design.

What You Will Learn

  • What are the technology drivers that are causing the need for more design verifications
  • What check automation of new physical design rules can be achieved
  • What are the expectations for verification standards driven by modern tools for Advanced Electrical Rule Checks

About the Presenter

Presenter Image Laurent Boganski

Laurent Boganski is a Product Specialist for Calibre solutions in interconnects parasitic extraction and Programmable Electrical Rule Checks. His responsibilities include supporting major customers in the area of physical verification, across Europe.

Laurent brings 20 years of experience in chip design and EDA tools support. He started his career as a design engineer at a gallium-arsenide foundry of Thales. Prior to joining Mentor 2 years ago, Laurent already worked in Grenoble at a major EDA vendor, in the area of parasitic extraction, and physical implementation of digital chips.

Laurent has an engineering degree in micro-electronics from ESIEE in Paris.

Who Should View

  • Design engineers
  • ESD protection engineers
  • Engineering managers

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