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CAA Using Calibre YieldAnalyzer: It's Not Just a Fab Problem Anymore

Overview

This session will address the need for critical area analysis (CAA) in the design process.  You will learn how Calibre Yield Analyzer supports several flows and capabilities that allow designers to get the details they need to create DFM-aware designs and enforce best practices across multiple design groups and IP providers.

At 45nm and beyond, foundries have made some DFM checks mandatory. Whether you are fabless, fab-lite, or IDM, the goal of reducing a design’s sensitivity to manufacturing issues should ideally be handled by the design teams. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing DFM problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

What You Will Learn

  • General theory and justification for CAA
  • Meaning of Defect Limited Yield (DLY)
  • Use CAA in a library & block/chip flow
  • Perform a memory redundancy analysis
  • Use RVE and DesignRev for batch reporting & design exploration

About the Presenter

Presenter Image Sjon Moore

Sjon Moore is a technical marketing engineer in the Integrated Electrical Systems Division (IESD) at Mentor Graphics. He joined the company in 2009 following his work on Freescale's Virtual Garage team. Sjon continues to work on the technologies acquired during Virtual Garage acquisition, helping to integrate these technologies into the current IESD product line. Before that, Sjon worked for more than 11 years as an automotive electrical systems engineer for tier 1 wiring suppliers, supporting many global automotive manufacturers.

Who Should View

  • Design Verification Engineers and Managers who want to own their DFM issues
  • Operations/Product Engineers and Managers

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